Merge pull request #117 from Bill94l/memoryMapping

Updating the memory mapping for SocDemo
SpinalHDL · Jul 17, 2024 · d6115eb · d6115eb
2 parents ba63ee6 + a0bd8ed
commit d6115eb
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala
@@ -75,7 +75,7 @@ class SocDemo(cpuCount : Int, withL2 : Boolean = true, asic : Boolean = false, x
  )
  )
  )
- emulated.node at(0, 0x1000) of bus
+ emulated.node at(0, 0x10000000) of bus
 
  val custom = Fiber build new Area{
  val mei,sei = in Bool()