Fix \= on reeg usages

SpinalHDL · Oct 25, 2023 · e2c46ef · e2c46ef
1 parent 1622bc2
commit e2c46ef
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/naxriscv/utilities/AllocatorMultiPort.scala b/src/main/scala/naxriscv/utilities/AllocatorMultiPort.scala
@@ -57,7 +57,7 @@ case class AllocatorMultiPortMem[T <: Data](dataType : HardType[T],
  }
 
  val pushArbitration = new Area{
- var pushOffset = ptr.push
+ var pushOffset = CombInit(ptr.push)
  val push = for(i <- 0 until pushCount) yield new Area{
  val ptr = CombInit(pushOffset)
  pushOffset \= pushOffset + io.push(i).valid.asUInt
@@ -85,7 +85,7 @@ case class AllocatorMultiPortMem[T <: Data](dataType : HardType[T],
 
 
  val popArbitration = new Area{
- var popOffset = ptr.pop
+ var popOffset = CombInit(ptr.pop)
  val pop = for(i <- 0 until popCount) yield new Area{
  val ptr = CombInit(popOffset)
  io.pop.values(i) := ways.map(_.pop.data).read(ptr(wayRange))