Revert unwanted push IBusDBusCachedTightlyCoupledRam

SpinalHDL · Apr 4, 2024 · 2cd19c8 · 2cd19c8
1 parent 7812bc6
commit 2cd19c8
Showing 1 changed file with 0 additions and 4 deletions.
diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -120,10 +120,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
  case _ =>
  }
 
- config.plugins += new IBusDBusCachedTightlyCoupledRam(
- mapping = SizeMapping(0x20000000, 0x1000)
- )
-
  val cpu = new VexRiscv(config)
  def doExport(value : => Any, postfix : String) = {
  sexport(Handle(value).setCompositeName(VexRiscvBmbGenerator.this, postfix))