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Disable LSU Cache on LiteX SoC

Status: Open.

#68 In SpinalHDL/VexiiRiscv;

· mkuhn99 opened on Aug 1, 2025

Create custom instructions that loads more than <code>LSLEN</code>

Status: Open.

#67 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Aug 1, 2025

CFU Examples or Docs?

Status: Open.

#62 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Jul 3, 2025

How to tunnel VexiiRiscv Debug port using BSCANE2?

Status: Open.

#58 In SpinalHDL/VexiiRiscv;

· Matze584 opened on May 27, 2025

[Feature Request] Vector extensions

Status: Open.

#57 In SpinalHDL/VexiiRiscv;

· jrmoserbaltimore opened on May 24, 2025

"Hello world" tutorial fails to compile

Status: Open.

#56 In SpinalHDL/VexiiRiscv;

· NikkiOfTheValley opened on May 23, 2025

Support for vectored interrupt mode?

Status: Open.

#53 In SpinalHDL/VexiiRiscv;

· Matze584 opened on Apr 20, 2025

How to extract RS1/RS2 value for debugging?

Status: Open.

#46 In SpinalHDL/VexiiRiscv;

· esyvjlomh opened on Mar 19, 2025

Is there anyway to generate with ICache and a extra cacheless I-channel？

Status: Open.

#39 In SpinalHDL/VexiiRiscv;

· HaroldZ32 opened on Jan 13, 2025

ti375 devkit litex debian demo

Status: Open.

#24 In SpinalHDL/VexiiRiscv;

· Dolu1990 opened on Sep 4, 2024

Roadmap / Contributing

Status: Open.

#1 In SpinalHDL/VexiiRiscv;

· Dolu1990 opened on Nov 14, 2023