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Run a simple bare metal program? #9
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original meaning VexRiscv ? It is probably a bit early if you think about FPGA / SoC, but for raw CPU simulation, i think it is good. I would say here : note that by default, most option / optimization for the CPU architecture are disabled. |
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Is this a better repo to use for simple experiments than the original?
I see there's a pointer to running the ELF simulation at this URL: https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/HowToUse/index.html
How/where do I supply my own code to generate an ELF for functional and performance evaluation?
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