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@RVECE-A-RISC-V-Community

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SudeepJoshi22/README.md
  • 👋 Hi, I’m @SudeepJoshi22
  • 👀 I’m interested in ... Computer Architecture, VLSI, and Analog Electronics
  • 🌱 I’m currently learning ... RISC-V ISA and Microarchitecures
  • 💞️ I’m looking to collaborate on ... RISC-V projects
  • 📫 How to reach me ... follow me on Linkedin: https://www.linkedin.com/in/sudeep-joshi-569951207/

Popular repositories Loading

  1. Minor-Project-2023-RISC-V-processor Minor-Project-2023-RISC-V-processor Public

    Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our…

    Verilog 9 1

  2. DHRUT-V DHRUT-V Public

    5-Stage Pipelined Custom RISC-V core

    Verilog 1

  3. SudeepJoshi22 SudeepJoshi22 Public

    Config files for my GitHub profile.

  4. CORDIC_Unit CORDIC_Unit Public

    CORDIC Unit Design and Synthesis Using Verilog HDL and YOSYS

    Python

  5. Qm.n-and-Integer-Interconversions Qm.n-and-Integer-Interconversions Public

    Signed Integer to Qm.n binary conversion and vice versa written in Python.

    Python

  6. Small_Projects Small_Projects Public

    C