OpenCL-Pipes

Implementing OpenCL Pipes for Rodinia applications on Xilinx FPGAs

This fork contains 2 parts.

1. OpenCL codes of a subset of Rodinia benchmark suite, version 3.1 ported and deployed on the AWS EC2 Cloud Xilinx VU9P FPGA. For the original benchmark page along with datasets and libs, refer here.

2. Optimised version of the above codes(kernel, host and makefile) using OpenCL Pipes run on the same FPGA platform.

Citation

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License

Copyright (c) 2019, University of North Carolina at Charlotte All rights reserved. - see the LICENSE file for details.