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use Yosys 0.39 #1848

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merged 7 commits into from
Mar 17, 2024
Merged

use Yosys 0.39 #1848

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6ec809b
use latest or
eder-matheus Mar 12, 2024
379a43d
use Yosys0.39
eder-matheus Mar 12, 2024
5f0a8fa
Merge branch 'master' into secure-yosys0.39
eder-matheus Mar 14, 2024
1c219e7
Merge branch 'master' into secure-yosys0.39
eder-matheus Mar 15, 2024
014eca6
Merge branch 'master' into secure-yosys0.39
eder-matheus Mar 17, 2024
76ac0bb
use latest or
eder-matheus Mar 17, 2024
9dbfc87
update public metrics
eder-matheus Mar 17, 2024
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538 changes: 269 additions & 269 deletions flow/designs/asap7/ibex/metadata-base-ok.json
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4 changes: 2 additions & 2 deletions flow/designs/asap7/ibex/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -230.49,
"value": -351.24,
"compare": ">="
},
"finish__design__instance__area": {
Expand All @@ -52,7 +52,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
"value": -11.34,
"value": -28.9,
"compare": ">="
}
}
546 changes: 273 additions & 273 deletions flow/designs/asap7/mock-alu/metadata-base-ok.json
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4 changes: 2 additions & 2 deletions flow/designs/asap7/mock-alu/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -28,15 +28,15 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 66023,
"value": 62749,
"compare": "<="
},
"detailedroute__route__drc_errors": {
"value": 0,
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -649.04,
"value": -693.46,
"compare": ">="
},
"finish__design__instance__area": {
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550 changes: 306 additions & 244 deletions flow/designs/gf180/ibex/metadata-base-ok.json
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18 changes: 9 additions & 9 deletions flow/designs/gf180/ibex/rules-base.json
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Original file line number Diff line number Diff line change
@@ -1,50 +1,50 @@
{
"synth__design__instance__area__stdcell": {
"value": 739750.9,
"value": 737573.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 775591,
"value": 757868,
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},
"placeopt__design__instance__count__stdcell": {
"value": 18839,
"value": 16247,
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"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1638,
"value": 1413,
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"cts__design__instance__count__hold_buffer": {
"value": 1638,
"value": 1413,
"compare": "<="
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"detailedroute__route__wirelength": {
"value": 1571453,
"value": 1484542,
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"detailedroute__route__drc_errors": {
"value": 0,
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"finish__timing__setup__ws": {
"value": -3.08,
"value": -3.85,
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"finish__design__instance__area": {
"value": 851353,
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"finish__timing__drv__setup_violation_count": {
"value": 819,
"value": 706,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
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2 changes: 1 addition & 1 deletion tools/OpenROAD
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Submodule OpenROAD updated 3 files
+2 −2 src/drt/src/io/io_parser_helper.cpp
+1 −0 src/gui/src/dbDescriptors.cpp
+4 −0 src/gui/src/gui.cpp
2 changes: 1 addition & 1 deletion tools/yosys
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Submodule yosys updated 85 files
+0 −1 .github/workflows/test-linux.yml
+1 −2 .github/workflows/test-macos.yml
+21 −0 CHANGELOG
+86 −89 Makefile
+8 −2 README.md
+20 −0 backends/aiger/aiger.cc
+3 −0 backends/blif/blif.cc
+9 −0 backends/cxxrtl/Makefile.inc
+180 −139 backends/cxxrtl/cxxrtl_backend.cc
+6 −6 backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+7 −2 backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+88 −27 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+117 −28 backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+3 −0 backends/edif/edif.cc
+3 −0 backends/firrtl/firrtl.cc
+4 −0 backends/json/json.cc
+12 −1 backends/smt2/smt2.cc
+85 −10 backends/smt2/smtbmc.py
+83 −12 backends/smt2/smtbmc_incremental.py
+97 −9 backends/smt2/smtio.py
+3 −0 backends/smv/smv.cc
+3 −0 backends/spice/spice.cc
+7 −0 backends/verilog/verilog_backend.cc
+1 −1 docs/source/CHAPTER_Basics.rst
+1 −1 docs/source/CHAPTER_CellLib.rst
+144 −0 examples/cxx-api/scopeinfo_example.cc
+37 −13 frontends/ast/ast.cc
+15 −7 frontends/ast/ast.h
+2 −2 frontends/ast/genrtlil.cc
+273 −357 frontends/ast/simplify.cc
+1 −0 frontends/verific/verific.cc
+25 −12 frontends/verilog/verilog_parser.y
+150 −7 kernel/celledges.cc
+1 −0 kernel/celltypes.h
+8 −1 kernel/driver.cc
+40 −0 kernel/register.cc
+9 −0 kernel/rtlil.cc
+1 −1 kernel/rtlil.h
+5 −0 kernel/satgen.cc
+129 −0 kernel/scopeinfo.cc
+432 −0 kernel/scopeinfo.h
+8 −20 kernel/yosys.cc
+2 −3 libs/ezsat/Makefile
+5 −6 libs/subcircuit/Makefile
+12 −7 misc/yosys-config.in
+15 −14 passes/cmds/connect.cc
+14 −1 passes/cmds/rename.cc
+27 −9 passes/cmds/show.cc
+21 −7 passes/cmds/stat.cc
+2 −0 passes/equiv/equiv_simple.cc
+3 −0 passes/memory/memory_collect.cc
+3 −0 passes/memory/memory_libmap.cc
+3 −0 passes/memory/memory_map.cc
+1 −1 passes/memory/memory_memx.cc
+3 −0 passes/memory/memory_narrow.cc
+5 −1 passes/memory/memory_share.cc
+9 −2 passes/opt/opt_clean.cc
+3 −0 passes/opt/opt_mem.cc
+3 −0 passes/opt/opt_merge.cc
+11 −5 passes/proc/proc_dlatch.cc
+5 −0 passes/proc/proc_rom.cc
+2 −1 passes/sat/clk2fflogic.cc
+2 −2 passes/sat/eval.cc
+1 −1 passes/techmap/Makefile.inc
+58 −23 passes/techmap/dfflibmap.cc
+96 −18 passes/techmap/flatten.cc
+2 −2 passes/techmap/techmap.cc
+7 −0 techlibs/common/simlib.v
+22 −3 techlibs/common/synth.cc
+2 −2 tests/gen-tests-makefile.sh
+23 −0 tests/proc/proc_rom.ys
+33 −2 tests/sat/sizebits.sv
+49 −0 tests/simple/arrays03.sv
+1 −0 tests/simple/memory.v
+21 −4 tests/sva/runtest.sh
+12 −0 tests/svtypes/multirange_array.sv
+45 −0 tests/svtypes/struct_array.sv
+25 −0 tests/svtypes/struct_sizebits.sv
+7 −0 tests/techmap/dfflibmap.ys
+1 −1 tests/unit/Makefile
+1 −0 tests/various/celledges_shift.ys
+20 −12 tests/various/clk2fflogic_effects.sh
+21 −2 tests/various/clk2fflogic_effects.sv
+110 −0 tests/various/scopeinfo.ys
+2 −1 tests/xprop/test.py
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