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Simplify handling of Liberty file related variables #2619

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4 changes: 2 additions & 2 deletions docs/user/FlowVariables.md
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ configuration file.
| <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | |
| <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | |
| <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | |
| <a name="DONT_USE_LIBS"></a>DONT_USE_LIBS| Set liberty files as `dont_use`.| | |
| <a name="LIB_FILES_EXTRACTED"></a>LIB_FILES| All technology mapping liberty files to use, extracted into object directory. Set by Makefile.| | |
| <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| |
| <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| |
| <a name="EQUIVALENCE_CHECK"></a>EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| |
Expand Down Expand Up @@ -334,7 +334,7 @@ configuration file.
- [DESIGN_NICKNAME](#DESIGN_NICKNAME)
- [DFF_LIB_FILES](#DFF_LIB_FILES)
- [DONT_USE_CELLS](#DONT_USE_CELLS)
- [DONT_USE_LIBS](#DONT_USE_LIBS)
- [LIB_FILES_EXTRACTED](#LIB_FILES_EXTRACTED)
- [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT)
- [ENABLE_DPO](#ENABLE_DPO)
- [FASTROUTE_TCL](#FASTROUTE_TCL)
Expand Down
17 changes: 10 additions & 7 deletions flow/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -286,9 +286,8 @@ WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.le
WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib))
export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)

export DONT_USE_LIBS = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS))
export LIB_FILES_EXTRACTED := $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
export SC_LIB_FILE ?= $(firstword $(LIB_FILES_EXTRACTED))

# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
STREAM_SYSTEM ?= GDS
Expand Down Expand Up @@ -355,12 +354,16 @@ versions.txt:
# Create temporary Liberty files which have the proper dont_use properties set
# For use with Yosys and ABC
.SECONDEXPANSION:
$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
$(LIB_FILES_EXTRACTED): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
@mkdir -p $(OBJECTS_DIR)/lib
$(UTILS_DIR)/preprocessLib.py -i $^ -o $@
@if echo "$<" | grep -q "\.gz$$"; then \
gunzip -c $< > $@; \
else \
cp $< $@; \
fi
Comment on lines +357 to +363
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Does Yosys support reading in compressed .gz files and decompressing on-the-fly? This step could be entirely eliminated if so.

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It does not, but it could. It requires zlib by default to support .fst wave files. I'll see what I can do

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I think it does when you supply the file to a frontend (e.g. read_liberty) but not e.g. in dfflibmap -liberty

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It would be nice to support gz in both

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We're working on it


$(OBJECTS_DIR)/lib/merged.lib:
$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(LIB_FILES_EXTRACTED) > $@

# Pre-process KLayout tech
# ==============================================================================
Expand Down Expand Up @@ -467,7 +470,7 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
mkdir -p $(dir $@)
echo $(ABC_CLOCK_PERIOD_IN_PS) > $@

YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
YOSYS_DEPENDENCIES=$(LIB_FILES_EXTRACTED) $(WRAPPED_LIBS) $(SC_LIB_FILE) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)

.PHONY: yosys-dependencies
yosys-dependencies: $(YOSYS_DEPENDENCIES)
Expand Down
2 changes: 1 addition & 1 deletion flow/platforms/asap7/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,7 @@ export LIB_FILES += $(ADDITIONAL_LIBS)
export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
export TEMPERATURE = $($(CORNER)_TEMPERATURE)
export VOLTAGE = $($(CORNER)_VOLTAGE)
export DONT_USE_SC_LIB = $(OBJECTS_DIR)/lib/merged.lib
export SC_LIB_FILE = $(OBJECTS_DIR)/lib/merged.lib

# ---------------------------------------------------------
# IR Drop
Expand Down
4 changes: 2 additions & 2 deletions flow/scripts/floorplan.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -126,7 +126,7 @@ if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {

write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v

restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \
restructure -target timing -liberty_file $::env(SC_LIB_FILE) \
-work_dir $::env(RESULTS_DIR)

write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v
Expand Down Expand Up @@ -171,7 +171,7 @@ if { [env_var_equals RESYNTH_AREA_RECOVER 1] } {
set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]

restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \
restructure -liberty_file $::env(SC_LIB_FILE) -target "area" \
-tiehi_port $tiehi_port \
-tielo_port $tielo_port \
-work_dir $::env(RESULTS_DIR)
Expand Down
2 changes: 1 addition & 1 deletion flow/scripts/synth.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ foreach cell $::env(DONT_USE_CELLS) {
if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
} else {
dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
dfflibmap -liberty $::env(SC_LIB_FILE) {*}$dfflibmap_args
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Same

}
opt

Expand Down
6 changes: 3 additions & 3 deletions flow/scripts/synth_preamble.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ foreach file $::env(VERILOG_FILES) {

# Read standard cells and macros as blackbox inputs
# These libs have their dont_use properties set accordingly
read_liberty -lib {*}$::env(DONT_USE_LIBS)
read_liberty -lib {*}$::env(LIB_FILES_EXTRACTED)

# Apply toplevel parameters (if exist)
if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
Expand Down Expand Up @@ -74,7 +74,7 @@ if {$::env(ABC_AREA)} {
# Technology mapping for cells
# ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
set abc_args [list -script $abc_script \
-liberty $::env(DONT_USE_SC_LIB) \
-liberty $::env(SC_LIB_FILE) \
-constr $::env(OBJECTS_DIR)/abc.constr]

# Exclude dont_use cells. This includes macros that are specified via
Expand All @@ -98,7 +98,7 @@ if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] && [file isfile $::env(

# Create argument list for stat
set stat_libs ""
foreach lib $::env(DONT_USE_LIBS) {
foreach lib $::env(LIB_FILES_EXTRACTED) {
append stat_libs "-liberty $lib "
}

Expand Down
2 changes: 1 addition & 1 deletion flow/scripts/synth_stats.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ proc write_keep_hierarchy {} {
if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
dfflibmap -liberty $::env(DFF_LIB_FILE)
} else {
dfflibmap -liberty $::env(DONT_USE_SC_LIB)
dfflibmap -liberty $::env(SC_LIB_FILE)
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The only reason for this if/else is because dfflibmap used to only take one liberty file. If it accepts multiple now, then you can simply pass in LIB_FILES_EXTRACTED and eliminate the DFF_LIB_FILE variable entirely. In fact, DFF_LIB_FILE was added exclusively to support ASAP7, no other PDK uses it.

}
puts "abc [join $abc_args " "]"
abc {*}$abc_args
Expand Down
6 changes: 3 additions & 3 deletions flow/scripts/variables.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ LIB_FILES:
input and output characteristics, timing and power definitions for each cell.
DONT_USE_CELLS:
description: >
Dont use cells eases pin access in detailed routing.
List of cells to mark dont_use to e.g. ease pin access in detailed routing.
SYNTH_GUT:
description: >
Load design and remove all internal logic before doing synthesis. This
Expand Down Expand Up @@ -547,9 +547,9 @@ CDL_FILES:
DFF_LIB_FILES:
description: >
Technology mapping liberty files for flip-flops.
DONT_USE_LIBS:
LIB_FILES_EXTRACTED:
description: >
Set liberty files as `dont_use`.
All technology mapping liberty files to use, extracted into object directory. Set by Makefile.
PRESERVE_CELLS:
description: >
Mark modules to keep from getting removed in flattening.
Expand Down
43 changes: 0 additions & 43 deletions flow/util/preprocessLib.py

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