Skip to content

Commit

Permalink
Added even more error checks and fixed str with shift hex gen
Browse files Browse the repository at this point in the history
  • Loading branch information
@TheTarados
TheTarados committed Nov 6, 2023
1 parent 8c27b67 commit f2dca8d
Show file tree
Hide file tree
Showing 4 changed files with 124 additions and 33 deletions.
98 changes: 80 additions & 18 deletions js/render_logic/armv4/armv4.js
View file
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,27 @@ class Armv4 extends Generic_logic {
for(let i = 0; i < this.code.length; i++){
let line = this.code[i];
let line_pos = this.code_lines[i];
let catched_error = false;
for (let i =0; i < line.length; i++){
let val = this.immediate_solver(line[i])

if(line[i][0] == "#"){
if(isNaN(val)){
show_error_message("Something beginning with # is not an immediate at line "+i, line_pos);
catched_error = true;
break;
}
if(val > 0xFFFFFFFF || val < 1-0x7FFFFFFF){
show_error_message("Immediate bigger than 32 bit value "+i, line_pos);
catched_error = true;
break;

}
}
}

if(catched_error)break;

let last_elem = line[line.length-1]

let op = this.get_operator(line[0])
Expand Down Expand Up @@ -228,10 +249,9 @@ class Armv4 extends Generic_logic {
show_error_message("Wrong number of arguments, "+ line.length+ " for op "+op.name+" at line " + i, line_pos);
break;
}
if(op.takes_label){//Check if every label argument to jump is valid
let label = last_elem;
if(!Object.keys(this.jmp_addr).includes(label) && label[0]!="#" && label[0]!="R" && label[0]!="]" && label[0]!="!"){
show_error_message("Label "+label+" not found at line " + i, line_pos);
if(op.takes_label && op.name[0] == "B"){//Check if every label argument to jump is valid
if (!Object.keys(this.jmp_addr).includes(last_elem) && last_elem[0]!="#"){
show_error_message("Wrong argument for B or label not recognized at line " + i, line_pos);
break;
}
}
Expand All @@ -242,7 +262,7 @@ class Armv4 extends Generic_logic {
}
for(let j = 2; j < line.length-1; j+=2){
if(!this.register_names.includes(line[j])){
show_error_message("Argument "+line[j]+" which should be a register is not a register: "+ line.join(" ")+" at line " + i, line_pos);
show_error_message("Argument "+line[j]+" which should be a register is not a register at line " + i, line_pos);
break;
}
if(!(line[j+1] == "," || line[j+1] == "-") && j != line.length-2){
Expand All @@ -257,7 +277,7 @@ class Armv4 extends Generic_logic {
}
}else if(op.name == "LDM" || op.name == "LDMIA" || op.name == "LDMFD"){
if(!this.register_names.includes(line[1])){
show_error_message("Argument "+line[1]+" which should be a register is not a register: "+ line.join(" ")+" at line " + i, line_pos);
show_error_message("Argument "+line[1]+" which should be a register is not a register at line " + i, line_pos);
break;
}
let W = line[2] == "!" ? 1 : 0;
Expand All @@ -267,31 +287,62 @@ class Armv4 extends Generic_logic {
}
for(let j = 4+W; j < line.length-1; j+=2){
if(!this.register_names.includes(line[j])){
show_error_message("Argument "+line[j]+" which should be a register is not a register: "+ line.join(" ")+" at line " + i, line_pos);
show_error_message("Argument "+line[j]+" which should be a register is not a register at line " + i, line_pos);
break;
}
if(!(line[j+1] == "," || line[j+1] == "-") && j != line.length-2){
show_error_message("Missing , or - between registers at line " + i, line_pos);
break;
}
}
}else if(!op.address_arg && op.name[0] != "B")
}else if(!op.address_arg && op.name[0] != "B"){
for(let j = 1; j < line.length; j+=2){ //Check if arguments are valid
if(line[j][0] == '#' && !(j ==line.length-1 && op.immediate_ok)){ //So only the second can be an immediate
show_error_message("Immediate argument in the wrong position: "+ line.join(" ")+" at line " + i, line_pos);
show_error_message("Immediate argument in the wrong position at line " + i, line_pos);
break;
}
if(line[j][0] != '#' && !this.register_names.includes(line[j])
&& !(shifts.includes(line[j])&& j==line.length-2) && !(line[j]=="RRX" && j==line.length-1)){
show_error_message("Argument "+line[j]+" which should be a register is not a register: "+ line.join(" ")+" at line " + i, line_pos);
show_error_message("Argument "+line[j]+" which should be a register is not a register: at line " + i, line_pos);
break;
}
if(line[j][0] == '#' && bit_size_shifted( Math.abs(this.immediate_solver(line[j]))) > (line[0]=="MOV"? 12: 8)){//Immediate respects bit limit
show_error_message("Immediate argument with too many bits (max 8 bit from highest to lowest for dp instr and 12 for mov): "+ line.join(" ")+" at line " + i, line_pos);
if(line[j][0] == '#' && bit_size_shifted( Math.abs(this.immediate_solver(line[j]))) > (op.name=="MOV"? 12: 8)){//Immediate respects bit limit
show_error_message("Immediate argument with too many bits (max 8 bit from highest to lowest for dp instr and 12 for mov) at line " + i, line_pos);
break;
}
}
else if(op.name[0] != "B"){//We're in a memory instruction
if(line.length == (op.name == "MOV"?6:8) && last_elem != "RRX"){
show_error_message("Problem at line, wrong number of element or RRX is badly writtin at " + i, line_pos);
}
if(line.length> 1 && last_elem != "RRX" && last_elem[0] != "#" && !this.register_names.includes(last_elem)){
show_error_message("Last element not recognized at line " + i, line_pos);
break;
}

if(shifts.includes(line[line.length -2])){
if(last_elem[0]!= "#"){
show_error_message("Shift must have an immediate argument " + i, line_pos);
break;
}
let val = this.immediate_solver(last_elem);
if(isNaN(val)){
show_error_message("Shift must have a correct immediate argument " + i, line_pos);
break;
}
if(val < 0){
show_error_message("Shift immediate must be positive " + i, line_pos);
break;
}
if(val > 32){
show_error_message("Shift instruction immediate shouldn't be bigger than 32 at line " + i, line_pos);
break;
}
if(["LSL", "ROR"].includes(line[line.length -2]) && val > 31){
show_error_message("LSL and ROR immediate shouldn't be bigger than 31 at line " + i, line_pos);
break;
}
}
}else if(op.name[0] != "B"){//We're in a memory instruction
//Get index of ]
let immediate_pos = 0;
let register_pos =0;
Expand Down Expand Up @@ -338,6 +389,7 @@ class Armv4 extends Generic_logic {
prob_with_addr ||= line[5] != "," ;
prob_with_addr ||= line[7] != "," ;
prob_with_addr ||= !shifts.includes(line[8]);
prob_with_addr ||= line[index-1][0] != "#";
register_pos = 6;
immediate_pos = 9;
break;
Expand Down Expand Up @@ -392,11 +444,21 @@ class Armv4 extends Generic_logic {
break;
}

if(immediate_pos > 0 && line[immediate_pos][0] == '#' //It is an immediate
&& bit_size( Math.abs(this.immediate_solver(line[immediate_pos]))) > 5 //Whose bits fits in 12
){
show_error_message("Immediate shift has too many bits (max 5 bit from highest to zeroth bit): "+ line.join(" ")+" at line " + i, line_pos);
break;
if(immediate_pos > 0 && line[immediate_pos][0] == '#'){ //It is an immediate
let val = this.immediate_solver(line[immediate_pos]);
if(val < 0){
show_error_message("Shift immediate must be positive " + i, line_pos);
break;
}
if(val > 32){
show_error_message("Shift immediate shouldn't be bigger than 32 at line " + i, line_pos);
break;
}
if(["LSL", "ROR"].includes(line[immediate_pos-1]) && val > 31){
show_error_message("LSL and ROR immediate shouldn't be bigger than 31 at line " + i, line_pos);
break;
}

}
}

Expand Down
31 changes: 18 additions & 13 deletions js/render_logic/armv4/instructions.js
View file
Original file line number Diff line number Diff line change
Expand Up @@ -569,9 +569,14 @@ class armv4_Memory_operator extends armv4_Operator{

//shamt5
let shamt5 = this.language.immediate_solver(elems[post_indexing?10:9]);
bin += get_unsigned_value(shamt5).toString(2).padStart(5, "0");
let shift_val = get_unsigned_value(shamt5);
bin += (shift_val%32).toString(2).padStart(5, "0");
//sh
bin += shift_to_sh[elems[post_indexing?9:8]];
if(shift_val == 0){
bin += "00"
}else{
bin += shift_to_sh[elems[post_indexing?9:8]];
}
} else if((elems[elems.length-2-pre_indexing] == "RRX")||
(elems[elems.length-1] == "RRX")){
//shamt5
Expand Down Expand Up @@ -707,7 +712,7 @@ class armv4_Operator_Lists{

let mov_operator = new armv4_Data_proc_operator("MOV", [4,6,7], (a,b,s, nzcv)=>{ return b; }, "1101", language);

let add_operator = new armv4_Data_proc_operator("ADD", [4,6,7, 9], (a,b,s, nzcv)=>{
let add_operator = new armv4_Data_proc_operator("ADD", [4,6,7,8,9], (a,b,s, nzcv)=>{
a = get_unsigned_value(a)
b = get_unsigned_value(b)
let sum = (a + b)&0xFFFFFFFF;
Expand All @@ -724,7 +729,7 @@ class armv4_Operator_Lists{
return sum;
}, "0100", language);

let adc_operator = new armv4_Data_proc_operator("ADC", [4,6,7, 9], (a,b,nzcv)=>{
let adc_operator = new armv4_Data_proc_operator("ADC", [4,6,7,8,9], (a,b,nzcv)=>{
a = get_unsigned_value(a)
b = get_unsigned_value(b)
let sum = (a+b+C)&0xFFFFFFFF;
Expand All @@ -740,7 +745,7 @@ class armv4_Operator_Lists{
return sum;
}, "0101", language);

let sub_operator = new armv4_Data_proc_operator("SUB", [4,6,7, 9], (a,b,s,nzcv)=>{
let sub_operator = new armv4_Data_proc_operator("SUB", [4,6,7,8,9], (a,b,s,nzcv)=>{
a = get_unsigned_value(a)
b = get_unsigned_value(b)
let not_b = ~b;
Expand All @@ -756,9 +761,9 @@ class armv4_Operator_Lists{
return sum;
}, "0010", language);

let rsub_operator = new armv4_Data_proc_operator("RSB", [4,6,7, 9], (a,b,s,nzcv)=>{ sub_operator.f(b,a,s)}, "0011");
let rsub_operator = new armv4_Data_proc_operator("RSB", [4,6,7,8,9], (a,b,s,nzcv)=>{ sub_operator.f(b,a,s)}, "0011");

let sbc_operator = new armv4_Data_proc_operator("SBC", [4,6,7, 9], (a,b,s,nzcv)=>{
let sbc_operator = new armv4_Data_proc_operator("SBC", [4,6,7,8,9], (a,b,s,nzcv)=>{
a = get_unsigned_value(a)
b = get_unsigned_value(b)
let not_b = ~b;
Expand All @@ -776,7 +781,7 @@ class armv4_Operator_Lists{
return sum;
}, "0110", language);

let rsc_operator = new armv4_Data_proc_operator("RSC", [4,6,7, 9], (a,b,s,nzcv)=>{ sbc_operator.f(b,a,s)}, "0111", language);
let rsc_operator = new armv4_Data_proc_operator("RSC", [4,6,7,8,9], (a,b,s,nzcv)=>{ sbc_operator.f(b,a,s)}, "0111", language);

let mul_operator = new armv4_Mul_operator("MUL", [4,6], (a,b,s,nzcv)=>{return (a*b)&0xFFFFFFFF;}, (a,b,c,d,s)=>{ return d; }, "000", language);

Expand All @@ -798,11 +803,11 @@ class armv4_Operator_Lists{
let umlal_operator = new armv4_Mul_operator("UMLAL", [8], (a,b,c,d,s)=>smlal_operator.f( a, get_unsigned_value(b), get_unsigned_value(c), d, s),
(a,b,c, d,s)=>smlal_operator.g( a, get_unsigned_value(b), get_unsigned_value(c), d, s), "101", language);

let and_operator = new armv4_Data_proc_operator("AND", [4,6,7, 9], (a,b,s,nzcv)=>{ return a&b; }, "0000", language);
let and_operator = new armv4_Data_proc_operator("AND", [4,6,7,8,9], (a,b,s,nzcv)=>{ return a&b; }, "0000", language);

let or_operator = new armv4_Data_proc_operator("ORR", [4,6,7,9], (a,b,s,nzcv)=>{ return a|b; }, "1100", language);
let or_operator = new armv4_Data_proc_operator("ORR", [4,6,7,8,9], (a,b,s,nzcv)=>{ return a|b; }, "1100", language);

let xor_operator = new armv4_Data_proc_operator("EOR", [4,6,7,9], (a,b,s,nzcv)=>{ return a^b; }, "0001", language);
let xor_operator = new armv4_Data_proc_operator("EOR", [4,6,7,8,9], (a,b,s,nzcv)=>{ return a^b; }, "0001", language);

//lsl
let lsl_operator = new armv4_Data_proc_operator("LSL", [4,6], (a,b,s,nzcv)=>{
Expand Down Expand Up @@ -843,9 +848,9 @@ class armv4_Operator_Lists{
rrx_operator.immediate_ok = false;

//bic
let bic_operator = new armv4_Data_proc_operator("BIC", [4,6,7,9], (a,b,s,nzcv)=>{return get_unsigned_value(a)&(~get_unsigned_value(b)); }, "1110", language);
let bic_operator = new armv4_Data_proc_operator("BIC", [4,6,7,8,9], (a,b,s,nzcv)=>{return get_unsigned_value(a)&(~get_unsigned_value(b)); }, "1110", language);
//mvn
let mvn_operator = new armv4_Data_proc_operator("MVN", [4,6,7,9], (a,b,s,nzcv)=>{ return ~b; }, "1111", language);
let mvn_operator = new armv4_Data_proc_operator("MVN", [4,6,7,8,9], (a,b,s,nzcv)=>{ return ~b; }, "1111", language);


//jump operator
Expand Down
14 changes: 13 additions & 1 deletion js/test/Armv4/codes/ref_input
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,4 +76,16 @@ add r0, r1, ror #0
add r0, r1, ror #1
strhs r0, [r1]
LDRSBls r0, [r1]
LDRSBls r0, [r1, r2]
LDRSBls r0, [r1, r2]
LDR R0, [R1], R2, LSR #32
LDR R0, [R1, R2, LSR #32]
LDR R0, [R1, R2, LSR #32]!
STR R0, [R1], R2, LSR #32
STR R0, [R1, R2, LSR #32]
STR R0, [R1, R2, LSR #32]!
LDR R0, [R1], R2, LSR #0
LDR R0, [R1, R2, LSR #0]
LDR R0, [R1, R2, LSR #0]!
STR R0, [R1], R2, LSR #0
STR R0, [R1, R2, LSR #0]
STR R0, [R1, R2, LSR #0]!
14 changes: 13 additions & 1 deletion js/test/Armv4/codes/ref_output
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,4 +76,16 @@ E0800001
E08000E1
25810000
91D100D0
919100D2
919100D2
E6910022
E7910022
E7B10022
E6810022
E7810022
E7A10022
E6910002
E7910002
E7B10002
E6810002
E7810002
E7A10002

0 comments on commit f2dca8d

Please sign in to comment.