Fix DIV, DIVU, REM, and REMU from setting fcsr

I'm not sure why I initially did this, its not in the
spec and its extra work. The values were correct and
come from the table in M extension

rars/riscv/instructions/DIV.java

@@ -39,12 +39,10 @@ public DIV() {
     public int compute(int value, int value2) {
         // Signal illegal division with -1
         if (value2 == 0) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x8); // Set Divide by Zero flag
             return -1;
         }
         // Overflow
         if (value == Integer.MIN_VALUE && value2 == -1) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x4); // Set Overflow flag
             return value;
         }
         return value / value2;

rars/riscv/instructions/DIVU.java

@@ -39,7 +39,6 @@ public DIVU() {
     public int compute(int value, int value2) {
         // Signal illegal division with -1
         if (value2 == 0) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x8); // Set Divide by Zero flag
             return -1;
         }
         return Integer.divideUnsigned(value, value2);

rars/riscv/instructions/REM.java

@@ -37,13 +37,12 @@ public REM() {
     }
 
     public int compute(int value, int value2) {
+        // Division by 0
         if (value2 == 0) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x8); // Set Divide by Zero flag
             return value;
         }
         // Overflow
         if (value == Integer.MIN_VALUE && value2 == -1) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x4); // Set Overflow flag
             return 0;
         }
         return value % value2;

rars/riscv/instructions/REMU.java

@@ -38,7 +38,6 @@ public REMU() {
 
     public int compute(int value, int value2) {
         if (value2 == 0) {
-            ControlAndStatusRegisterFile.orRegister("fcsr", 0x8); // Set Divide by Zero flag
             return value;
         }
         return Integer.remainderUnsigned(value, value2);