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I believe these work, but I haven't written test benches yet. Mainly posting them here so that they're there, and perhaps as a starting point towards merging it.
I expect you'd want test benches before you merge it, but I have almost no experience with Verilog and don't know that I'm well-suited to do it. Perhaps you could point me in the right direction?
Also I think the 74244 would probably want to use 2 BLOCKS of WIDTH 4, instead of WIDTH = 8.
Thanks for making this repo, it is very helpful. I'm using it to help design a CPU: https://github.com/jes/ttl-cpu - I do have a test bench system in that repo but it is very ad-hoc and bad. It is quite possible that I'll be creating more 74xx chips.