pg: Add basic modeling of the power gate behavior

Useful for GL simulation where without this the user module end up not powered and everything fails. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
TinyTapeout · Mar 13, 2024 · 6efa0f9 · 6efa0f9
1 parent 76803d3
commit 6efa0f9
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diff --git a/pg/tt_pg_vdd_1/tt_pg_vdd_1.v b/pg/tt_pg_vdd_1/tt_pg_vdd_1.v
@@ -17,4 +17,8 @@ module tt_pg_vdd_1 (
 	input  wire ctrl
 );
 
+`ifdef USE_POWER_PINS
+	assign GPWR = !ctrl ? VPWR : 1'bz;
+`endif
+
 endmodule
diff --git a/pg/tt_pg_vdd_2/tt_pg_vdd_2.v b/pg/tt_pg_vdd_2/tt_pg_vdd_2.v
@@ -17,4 +17,8 @@ module tt_pg_vdd_2 (
 	input  wire ctrl
 );
 
+`ifdef USE_POWER_PINS
+	assign GPWR = !ctrl ? VPWR : 1'bz;
+`endif
+
 endmodule