Merge pull request #1424 from TomHarte/InstructionSetFormatting

Improve formatting, `const`ness in instruction sets.

Analyser/Static/AppleII/Target.hpp

@@ -50,7 +50,7 @@ struct Target: public Analyser::Static::Target, public Reflection::StructImpl<Ta
 	}
 };
 
-constexpr bool is_iie(Target::Model model) {
+constexpr bool is_iie(const Target::Model model) {
 	return model == Target::Model::IIe || model == Target::Model::EnhancedIIe;
 }
 

Components/6845/CRTC6845.hpp

@@ -43,7 +43,7 @@ enum class Personality {
 	EGA,		// Extended EGA-style CRTC; uses 16-bit addressing throughout.
 };
 
-constexpr bool is_egavga(Personality p) {
+constexpr bool is_egavga(const Personality p) {
 	return p >= Personality::EGA;
 }
 

Components/8272/Results.hpp

@@ -52,7 +52,7 @@ class Results {
 	}
 
 	/// @returns @c true if all result bytes are exhausted; @c false otherwise.
-	bool empty() const 	{	return result_.empty();	}
+	bool empty() const	{	return result_.empty();	}
 
 	/// @returns The next byte of the result.
 	uint8_t next() {

Components/8272/Status.hpp

@@ -38,7 +38,7 @@ enum class Status0: uint8_t {
 
 enum class Status1: uint8_t {
 	EndOfCylinder		= 0x80,
-	DataError 			= 0x20,
+	DataError			= 0x20,
 	OverRun				= 0x10,
 	NoData				= 0x04,
 	NotWriteable		= 0x02,
@@ -47,7 +47,7 @@ enum class Status1: uint8_t {
 
 enum class Status2: uint8_t {
 	DeletedControlMark		= 0x40,
-	DataCRCError 			= 0x20,
+	DataCRCError			= 0x20,
 	WrongCyinder			= 0x10,
 	ScanEqualHit			= 0x08,
 	ScanNotSatisfied		= 0x04,
@@ -57,7 +57,7 @@ enum class Status2: uint8_t {
 
 enum class Status3: uint8_t {
 	Fault				= 0x80,
-	WriteProtected 		= 0x40,
+	WriteProtected		= 0x40,
 	Ready				= 0x20,
 	Track0				= 0x10,
 	TwoSided			= 0x08,
@@ -91,9 +91,9 @@ class Status {
 	void set(const MainStatus flag, const bool value) {
 		set(uint8_t(flag), value, main_status_);
 	}
-	void start_seek(const int drive) 	{	main_status_ |= 1 << drive;	}
+	void start_seek(const int drive)	{	main_status_ |= 1 << drive;	}
 	void set(const Status0 flag)		{	set(uint8_t(flag), true, status_[0]);	}
-	void set(const Status1 flag)	 	{	set(uint8_t(flag), true, status_[1]);	}
+	void set(const Status1 flag)		{	set(uint8_t(flag), true, status_[1]);	}
 	void set(const Status2 flag)		{	set(uint8_t(flag), true, status_[2]);	}
 
 	void set_status0(uint8_t value)	{	status_[0] = value;	}

InstructionSets/ARM/BarrelShifter.hpp

@@ -31,7 +31,7 @@ template <> struct Carry<false> {
 ///
 /// Shift amounts of 0 are given the meaning attributed to them for immediate shift counts.
 template <ShiftType type, bool set_carry, bool is_immediate_shift>
-void shift(uint32_t &source, uint32_t amount, typename Carry<set_carry>::type carry) {
+void shift(uint32_t &source, uint32_t amount, const typename Carry<set_carry>::type carry) {
 	switch(type) {
 		case ShiftType::LogicalLeft:
 			if(amount > 32) {
@@ -113,7 +113,7 @@ void shift(uint32_t &source, uint32_t amount, typename Carry<set_carry>::type ca
 
 /// Acts as per @c shift above, but applies runtime shift-type selection.
 template <bool set_carry, bool is_immediate_shift>
-void shift(ShiftType type, uint32_t &source, uint32_t amount, typename Carry<set_carry>::type carry) {
+void shift(const ShiftType type, uint32_t &source, const uint32_t amount, const typename Carry<set_carry>::type carry) {
 	switch(type) {
 		case ShiftType::LogicalLeft:
 			shift<ShiftType::LogicalLeft, set_carry, is_immediate_shift>(source, amount, carry);

InstructionSets/ARM/Disassembler.hpp

@@ -74,7 +74,7 @@ struct Instruction {
 	bool sets_flags = false;
 	bool is_byte = false;
 
-	std::string to_string(uint32_t address) const {
+	std::string to_string(const uint32_t address) const {
 		std::ostringstream result;
 
 		// Treat all nevers as nops.
@@ -161,17 +161,17 @@ struct Instruction {
 /// able to vend it later via @c last().
 template <Model model>
 struct Disassembler {
-	Instruction last() {
+	Instruction last() const {
 		return instruction_;
 	}
 
-	bool should_schedule(Condition condition) {
+	bool should_schedule(const Condition condition) {
 		instruction_ = Instruction();
 		instruction_.condition = condition;
 		return true;
 	}
 
-	template <Flags f> void perform(DataProcessing fields) {
+	template <Flags f> void perform(const DataProcessing fields) {
 		constexpr DataProcessingFlags flags(f);
 
 		instruction_.operand1.type = Operand::Type::Register;
@@ -214,7 +214,7 @@ struct Disassembler {
 	}
 
 	template <Flags> void perform(Multiply) {}
-	template <Flags f> void perform(SingleDataTransfer fields) {
+	template <Flags f> void perform(const SingleDataTransfer fields) {
 		constexpr SingleDataTransferFlags flags(f);
 		instruction_.operation =
 			(flags.operation() == SingleDataTransferFlags::Operation::STR) ?
@@ -226,7 +226,7 @@ struct Disassembler {
 		instruction_.operand1.type = Operand::Type::Register;
 		instruction_.operand1.value = fields.base();
 	}
-	template <Flags f> void perform(BlockDataTransfer fields) {
+	template <Flags f> void perform(const BlockDataTransfer fields) {
 		constexpr BlockDataTransferFlags flags(f);
 		instruction_.operation =
 			(flags.operation() == BlockDataTransferFlags::Operation::STM) ?
@@ -238,7 +238,7 @@ struct Disassembler {
 		instruction_.operand1.type = Operand::Type::RegisterList;
 		instruction_.operand1.value = fields.register_list();
 	}
-	template <Flags f> void perform(Branch fields) {
+	template <Flags f> void perform(const Branch fields) {
 		constexpr BranchFlags flags(f);
 		instruction_.operation =
 			(flags.operation() == BranchFlags::Operation::BL) ?
@@ -264,7 +264,6 @@ struct Disassembler {
 
 private:
 	Instruction instruction_;
-
 };
 
 }

InstructionSets/ARM/Executor.hpp

@@ -18,7 +18,7 @@ namespace InstructionSet::ARM {
 /// Maps from a semantic ARM read of type @c SourceT to either the 8- or 32-bit value observed
 /// by watching the low 8 bits or all 32 bits of the data bus.
 template <typename DestinationT, typename SourceT>
-DestinationT read_bus(SourceT value) {
+DestinationT read_bus(const SourceT value) {
 	if constexpr (std::is_same_v<DestinationT, SourceT>) {
 		return value;
 	}
@@ -57,14 +57,14 @@ struct Executor {
 
 	/// @returns @c true if @c condition implies an appropriate perform call should be made for this instruction,
 	/// @c false otherwise.
-	bool should_schedule(Condition condition) {
+	bool should_schedule(const Condition condition) {
 		// This short-circuit of registers_.test provides the necessary compiler clue that
 		// Condition::AL is not only [[likely]] but [[exceedingly likely]].
 		return condition == Condition::AL ? true : registers_.test(condition);
 	}
 
 	template <bool allow_register, bool set_carry, typename FieldsT>
-	uint32_t decode_shift(FieldsT fields, uint32_t &rotate_carry, uint32_t pc_offset) {
+	uint32_t decode_shift(const FieldsT fields, uint32_t &rotate_carry, const uint32_t pc_offset) {
 		// "When R15 appears in the Rm position it will give the value of the PC together
 		// with the PSR flags to the barrel shifter. ...
 		//
@@ -105,7 +105,7 @@ struct Executor {
 		return operand2;
 	}
 
-	template <Flags f> void perform(DataProcessing fields) {
+	template <Flags f> void perform(const DataProcessing fields) {
 		constexpr DataProcessingFlags flags(f);
 		const bool shift_by_register = !flags.operand2_is_immediate() && fields.shift_count_is_register();
 
@@ -142,7 +142,10 @@ struct Executor {
 		const auto sub = [&](uint32_t lhs, uint32_t rhs) {
 			conditions = lhs - rhs;
 
-			if constexpr (flags.operation() == DataProcessingOperation::SBC || flags.operation() == DataProcessingOperation::RSC) {
+			if constexpr (
+				flags.operation() == DataProcessingOperation::SBC ||
+				flags.operation() == DataProcessingOperation::RSC
+			) {
 				conditions += registers_.c() - 1;
 			}
 
@@ -225,7 +228,7 @@ struct Executor {
 		}
 	}
 
-	template <Flags f> void perform(Multiply fields) {
+	template <Flags f> void perform(const Multiply fields) {
 		constexpr MultiplyFlags flags(f);
 
 		// R15 rules:
@@ -252,7 +255,7 @@ struct Executor {
 		}
 	}
 
-	template <Flags f> void perform(Branch branch) {
+	template <Flags f> void perform(const Branch branch) {
 		constexpr BranchFlags flags(f);
 
 		if constexpr (flags.operation() == BranchFlags::Operation::BL) {
@@ -261,7 +264,7 @@ struct Executor {
 		set_pc<true>(registers_.pc(4) + branch.offset());
 	}
 
-	template <Flags f> void perform(SingleDataTransfer transfer) {
+	template <Flags f> void perform(const SingleDataTransfer transfer) {
 		constexpr SingleDataTransferFlags flags(f);
 
 		// Calculate offset.
@@ -386,7 +389,7 @@ struct Executor {
 			}
 		}
 	}
-	template <Flags f> void perform(BlockDataTransfer transfer) {
+	template <Flags f> void perform(const BlockDataTransfer transfer) {
 		constexpr BlockDataTransferFlags flags(f);
 		constexpr bool is_ldm = flags.operation() == BlockDataTransferFlags::Operation::LDM;
 
@@ -573,7 +576,7 @@ struct Executor {
 		}
 	}
 
-	void software_interrupt(SoftwareInterrupt swi) {
+	void software_interrupt(const SoftwareInterrupt swi) {
 		if(control_flow_handler_.should_swi(swi.comment())) {
 			exception<Registers::Exception::SoftwareInterrupt>();
 		}
@@ -614,7 +617,7 @@ struct Executor {
 	///
 	/// By default this is not forwarded to the control-flow handler.
 	template <bool notify = false>
-	void set_pc(uint32_t pc) {
+	void set_pc(const uint32_t pc) {
 		registers_.set_pc(pc);
 		if constexpr (notify) {
 			control_flow_handler_.did_set_pc();
@@ -637,7 +640,7 @@ struct Executor {
 		control_flow_handler_.did_set_pc();
 	}
 
-	void set_status(uint32_t status) {
+	void set_status(const uint32_t status) {
 		registers_.set_status(status);
 		control_flow_handler_.did_set_status();
 	}
@@ -650,7 +653,7 @@ struct Executor {
 	ControlFlowHandlerTStorage control_flow_handler_;
 	Registers registers_;
 
-	static bool is_invalid_address(uint32_t address) {
+	static bool is_invalid_address(const uint32_t address) {
 		if constexpr (model == Model::ARMv2with32bitAddressing) {
 			return false;
 		}
@@ -661,7 +664,7 @@ struct Executor {
 /// Executes the instruction @c instruction which should have been fetched from @c executor.pc(),
 /// modifying @c executor.
 template <Model model, typename MemoryT, typename StatusObserverT>
-void execute(uint32_t instruction, Executor<model, MemoryT, StatusObserverT> &executor) {
+void execute(const uint32_t instruction, Executor<model, MemoryT, StatusObserverT> &executor) {
 	executor.set_pc(executor.pc() + 4);
 	dispatch<model>(instruction, executor);
 }