Adding expressions for unary reduction operators added in VHDL-2008

VHDL · Sep 26, 2024 · 169d548 · 169d548
1 parent 7a63b07
commit 169d548
Showing 1 changed file with 30 additions and 0 deletions.
diff --git a/pyVHDLModel/Expression.py b/pyVHDLModel/Expression.py
@@ -257,6 +257,36 @@ class InverseExpression(UnaryExpression):
  _FORMAT = ("not ", "")
 
 
+@export
+class UnaryAndExpression(UnaryExpression):
+ _FORMAT = ("and ", "")
+
+
+@export
+class UnaryNandExpression(UnaryExpression):
+ _FORMAT = ("nand ", "")
+
+
+@export
+class UnaryOrExpression(UnaryExpression):
+ _FORMAT = ("or ", "")
+
+
+@export
+class UnaryNorExpression(UnaryExpression):
+ _FORMAT = ("nor ", "")
+
+
+@export
+class UnaryXorExpression(UnaryExpression):
+ _FORMAT = ("xor ", "")
+
+
+@export
+class UnaryXnorExpression(UnaryExpression):
+ _FORMAT = ("xnor ", "")
+
+
 @export
 class AbsoluteExpression(UnaryExpression):
  _FORMAT = ("abs ", "")