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Adding resolution of record element subtypes in packages #78

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merged 8 commits into from
Jun 8, 2024

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Tcenova
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@Tcenova Tcenova commented Jun 7, 2024

New Features

  • Record element subtypes are now resolved in packages

@Paebbels Paebbels self-requested a review June 8, 2024 03:59
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LGTM.

@Paebbels Paebbels changed the base branch from main to dev June 8, 2024 04:10
@Paebbels Paebbels merged commit 7c01493 into VHDL:dev Jun 8, 2024
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Paebbels commented Jun 8, 2024

@Tcenova do you need this change to be released as v0.29.0 or is a merge to dev branch ok so far?

Currently, dev branch has only a few changes.

@Paebbels Paebbels mentioned this pull request Jun 8, 2024
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Tcenova commented Jun 8, 2024

The dev branch is fine for now. I am waiting on your changes in the standalone branch of ghdl to make there way to master before it would be useful. I have been testing with a combination of branches of things to get type resolution working. Its also possible I may have other pull requests in the future if I implement other missing pieces.

@Tcenova Tcenova deleted the add-record-subtype-parsing branch June 8, 2024 15:03
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Paebbels commented Jun 9, 2024

I am waiting on your changes in the standalone branch of ghdl to make there way to master before it would be useful.

Are you waiting because of the standalone installation feature or because of gathered additions to GHDL?

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Paebbels commented Jun 9, 2024

May I asked if the pyVHDLModel is so far understandable. It doesn't have lots of documentation and it might not be easy to understand what I did and how I did it :).

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Tcenova commented Jun 10, 2024

I am waiting on your changes in the standalone branch of ghdl to make there way to master before it would be useful.

Are you waiting because of the standalone installation feature or because of gathered additions to GHDL?

I am mainly waiting on the changes to pyGHDL that allow it to use the latest version of pyVHDLModel. Overall, I am trying to fully parse an entities ports and generics. I have some local code to also resolve subtypes of the ports which is only possible with the latest code. I am also trying to extract the constraints of ports and generics on an entity, hence why I opened ghdl/ghdl#2661

May I asked if the pyVHDLModel is so far understandable. It doesn't have lots of documentation and it might not be easy to understand what I did and how I did it :).

I cant say I have been able to understand the high level approach/reasoning for things yet, but I also haven't spent much time trying. There seems to be many layers, along with more layers added in the DOM in pyGHDL, so traversing through the layers has sometimes been a challenge. I am able to generally understand how to use things after looking at the different layers of source code though.

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Paebbels commented Jun 10, 2024

Oh, ghdl/ghdl#2661. I didn't recognize your name from there. Sorry.

I'll try to invest more time into it. (pending PR: ghdl/ghdl#2439)

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