Removed acceptance testing issues with Riviera-PRO, Active-HDL and Mo…

…delsim.

tests/acceptance/test_artificial.py

@@ -25,8 +25,12 @@ class TestVunitArtificial(unittest.TestCase):
     """
 
     def setUp(self):
-        # Spaces in path intentional to verify that it is supported
-        self.output_path = join(dirname(__file__), "artificial _out")
+        if simulator_is("activehdl"):
+            self.output_path = join(dirname(__file__), "artificial_out")
+        else:
+            # Spaces in path intentional to verify that it is supported
+            self.output_path = join(dirname(__file__), "artificial _out")
+
         self.report_file = join(self.output_path, "xunit.xml")
         self.artificial_run_vhdl = join(
             dirname(__file__), "artificial", "vhdl", "run.py"

tests/acceptance/test_external_run_scripts.py

@@ -146,6 +146,9 @@ def test_vhdl_composite_generics_example_project(self):
             ],
         )
 
+    @unittest.skipUnless(
+        simulator_is("ghdl"), "Support complex JSON strings as generic"
+    )
     def test_vhdl_json4vhdl_example_project(self):
         self.check(join(ROOT, "examples", "vhdl", "json4vhdl", "run.py"))
 

vunit/vhdl/data_types/src/string_ptr_pkg-body-93.vhd

@@ -198,7 +198,7 @@ package body string_ptr_pkg is
 
   procedure reallocate (
     ptr   : ptr_t;
-    value : string
+    value : vec_t
   ) is
     variable s : storage_t := st.idxs(ptr.ref);
     variable n_value : string(1 to value'length) := value;

vunit/vhdl/data_types/src/types.vhd

@@ -30,8 +30,7 @@ package types_pkg is
   type integer_vector_access_vector_t is array (natural range <>) of integer_vector_access_t;
   type integer_vector_access_vector_access_t is access integer_vector_access_vector_t;
 
-  type extintvec_access_t is access integer_vector_t(0 to integer'high-1);
+  type extintvec_access_t is access integer_vector_t(0 to integer'high / 2 - 1);
   type extintvec_access_vector_t is array (natural range <>) of extintvec_access_t;
   type extintvec_access_vector_access_t is access extintvec_access_vector_t;
 end package;
-

vunit/vhdl/logging/test/tb_deprecated.vhd

@@ -172,7 +172,7 @@ begin
         mock(default_logger);
         verbose("hello", 17, "foo.vhd");
         check_log(default_logger, "Mapping deprecated procedure verbose to trace", warning);
-        check_log(default_logger, "hello", verbose, 0 ns, 17, "foo.vhd");
+        check_log(default_logger, "hello", trace, 0 ns, 17, "foo.vhd");
         unmock(default_logger);
 
       end if;

vunit/vhdl/run/test/tb_watchdog.vhd

@@ -28,13 +28,10 @@ begin
     if run("test watchdog no timeout") then
       wait for 1 ns;
 
-    elsif run("Test timeout notification") then
-      wait until timeout_notification(runner);
-      check_equal(now, 2 ns);
-
-    elsif run("test watchdog timeout") then
+    elsif run("Test watchdog timeout") then
       mock(runner_trace_logger, error);
       wait until timeout_notification(runner);
+      check_equal(now, 2 ns);
       wait for 1 ps;
       check_only_log(runner_trace_logger, "Test runner timeout after " & time'image(2 ns) & ".", error, 2 ns);
       unmock(runner_trace_logger);