add JSON-for-VHDL

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "vunit/vhdl/osvvm"]
 	path = vunit/vhdl/osvvm
-	url = https://github.com/OSVVM/OSVVM.git
+	url = https://github.com/OSVVM/OSVVM.git
+[submodule "vunit/vhdl/JSON-for-VHDL"]
+	path = vunit/vhdl/JSON-for-VHDL
+	url = https://github.com/Paebbels/JSON-for-VHDL.git

docs/user_guide.rst

@@ -233,3 +233,11 @@ There are many examples demonstrating more specific usage of VUnit listed below:
   Demonstrates the ``com`` message passing package which can be used
   to communicate arbitrary objects between processes.  Further reading
   can be found in the :ref:`com user guide <com_user_guide>`
+
+:vunit_example:`Composite generics <vhdl/composite_generics>`
+  See `Enable Your Simulator to Handle Complex Top-Level Generics <https://vunit.github.io/posts/2017_06_03_enable_your_simulator_to_handle_complex_top_level_generics/post.html>`_
+
+:vunit_example:`JSON-for-VHDL example <vhdl/json4vhdl>`
+  Demonstrates the ``JSON-for-VHDL`` library which can be used to parse JSON content.
+  The content can be read from a file, or passed as a stringified generic.
+  This is an alternative to composite generics, that supports any depth in the content structure.

examples/vhdl/json4vhdl/run.py

@@ -0,0 +1,23 @@
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v. 2.0. If a copy of the MPL was not distributed with this file,
+# You can obtain one at http://mozilla.org/MPL/2.0/.
+#
+# Copyright (c) 2014-2018, Lars Asplund lars.anders.asplund@gmail.com
+
+from os.path import join, dirname
+from vunit import VUnit
+
+root = dirname(__file__)
+
+vu = VUnit.from_argv()
+
+vu.add_json4vhdl()
+
+lib = vu.add_library("test")
+lib.add_source_files(join(root, "src/test/*.vhd"))
+
+import json
+generics = json.loads(open(join(root, "src/test/data/data.json"), 'r').read())
+vu.set_json_generic("tb_cfg", generics )
+
+vu.main()

examples/vhdl/json4vhdl/src/test/data/data.json

@@ -0,0 +1,19 @@
+{
+	"Image": [640, 480],
+	"Platform": {
+		"ML505": {
+			"FPGA": "XC5VLX50T-1FF1136"
+		},
+		"KC705": {
+			"FPGA": "XC7K325T-2FFG900C",
+			"IIC": [{
+				"Type": "Switch",
+				"Adr": "0x85",
+				"Devices": [{
+					"Name": "Si570",
+					"Address": "0x3A"
+				}]
+			}]
+		}
+	}
+}

examples/vhdl/json4vhdl/src/test/tb_json_gens.vhd

@@ -0,0 +1,47 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2018, Lars Asplund lars.anders.asplund@gmail.com
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+library vunit_lib;
+use vunit_lib.json.T_JSON;
+use vunit_lib.json.jsonLoad;
+use vunit_lib.json.jsonGetString;
+
+entity tb_json_gens is
+  generic (
+    runner_cfg  : string;
+    tb_path     : string;
+    tb_cfg      : string;
+    tb_cfg_file : string := "data/data.json"
+  );
+end entity;
+
+architecture tb of tb_json_gens is
+  constant JSONContent     : T_JSON := jsonLoad(tb_cfg);
+  constant JSONFileContent : T_JSON := jsonLoad(tb_path & tb_cfg_file);
+begin
+  main: process
+  begin
+    test_runner_setup(runner, runner_cfg);
+    while test_suite loop
+      if run("test") then
+        info("JSONContent: " & lf & JSONContent.Content);
+        info("Image: " & jsonGetString(JSONContent, "Image/0") & ',' & jsonGetString(JSONContent, "Image/1"));
+        info("Platform/ML505/FPGA: " & jsonGetString(JSONContent, "Platform/ML505/FPGA"));
+        info("Platform/KC705/IIC/0/Devices/0/Name: " & jsonGetString(JSONContent, "Platform/KC705/IIC/0/Devices/0/Name"));
+
+        info("tb_path & tb_cfg_file: " & tb_path & tb_cfg_file);
+        info("JSONFileContent: " & lf & JSONFileContent.Content);
+        info("Image: " & jsonGetString(JSONFileContent, "Image/0") & ',' & jsonGetString(JSONFileContent, "Image/1"));
+        info("Platform/ML505/FPGA: " & jsonGetString(JSONFileContent, "Platform/ML505/FPGA"));
+        info("Platform/KC705/IIC/0/Devices/0/Name: " & jsonGetString(JSONFileContent, "Platform/KC705/IIC/0/Devices/0/Name"));
+      end if;
+    end loop;
+    test_runner_cleanup(runner);
+    wait;
+  end process;
+end architecture;

vunit/builtins.py

@@ -35,6 +35,7 @@ def add(name, deps=tuple()):
         add("verification_components", ["com", "osvvm"])
         add("osvvm")
         add("random", ["osvvm"])
+        add("json4vhdl")
 
     def add(self, name, args=None):
         self._builtins_adder.add(name, args)
@@ -147,6 +148,19 @@ def _add_osvvm(self):
 
             library.add_source_files(file_name, preprocessors=[])
 
+    def _add_json4vhdl(self):
+        """
+        Add JSON-for-VHDL library
+        """
+        library_name = "vunit_lib"
+
+        try:
+            library = self._vunit_obj.library(library_name)
+        except KeyError:
+            library = self._vunit_obj.add_library(library_name)
+
+        library.add_source_files(join(VHDL_PATH, "JSON-for-VHDL", "vhdl", "*.vhdl"))
+
     def add_verilog_builtins(self):
         """
         Add Verilog builtins

vunit/test/acceptance/test_external_run_scripts.py

@@ -102,6 +102,9 @@ def test_vhdl_composite_generics_example_project(self):
                      [("passed", "tb_lib.tb_composite_generics.VGA.Test 1"),
                       ("passed", "tb_lib.tb_composite_generics.tiny.Test 1")])
 
+    def test_vhdl_json4vhdl_example_project(self):
+        self.check(join(ROOT, "examples", "vhdl", "json4vhdl", "run.py"))
+
     def test_vhdl_array_example_project(self):
         self.check(join(ROOT, "examples", "vhdl", "array", "run.py"))
 

vunit/test/lint/test_license.py

@@ -106,6 +106,8 @@ def find_licensed_files():
     Return all licensed files
     """
     licensed_files = []
+    osvvm_directory = abspath(join(VHDL_PATH, 'osvvm'))
+    json4vhdl_directory = abspath(join(VHDL_PATH, 'JSON-for-VHDL'))
     for root, _, files in walk(ROOT):
         for file_name in files:
             if 'preprocessed' in root:
@@ -116,9 +118,10 @@ def find_licensed_files():
                 continue
             if join(ROOT, ".tox") in root:
                 continue
-            osvvm_directory = abspath(join(VHDL_PATH, 'osvvm'))
             if is_prefix_of(osvvm_directory, abspath(join(root, file_name))):
                 continue
+            if is_prefix_of(json4vhdl_directory, abspath(join(root, file_name))):
+                continue
             if splitext(file_name)[1] in ('.vhd', '.vhdl', '.py', '.v', '.sv'):
                 licensed_files.append(join(root, file_name))
     return licensed_files

vunit/ui.py

@@ -447,6 +447,26 @@ def set_generic(self, name, value, allow_empty=False):
         for test_bench in check_not_empty(test_benches, allow_empty, "No test benches found"):
             test_bench.set_generic(name.lower(), value)
 
+    def set_json_generic(self, name, value, allow_empty=False):
+        """
+        Set a value of stringified JSON generic in all |configurations|
+
+        :param name: The name of the generic
+        :param value: The value of the object to be stringified
+        :param allow_empty: To disable an error when no test benches were found
+
+        :example:
+
+        .. code-block:: python
+
+           prj.set_generic("tb_cfg", json.loads(open(join(root, "cfg.json"), 'r').read()))
+
+        .. note::
+           Only affects test benches added *before* the generic is set.
+        """
+        import json
+        self.set_generic(name, json.dumps(value, separators=(',', ':')), allow_empty)
+
     def set_parameter(self, name, value, allow_empty=False):
         """
         Set value of parameter in all |configurations|
@@ -933,6 +953,12 @@ def add_osvvm(self):
         """
         self._builtins.add("osvvm")
 
+    def add_json4vhdl(self):
+        """
+        Add JSON-for-VHDL library
+        """
+        self._builtins.add("json4vhdl")
+
     def get_compile_order(self, source_files=None):
         """
         Get the compile order of all or specific source files and