Verilog parser invalid handling of whitespace can miss newlines

[haggaie]

When parsing the `timescale command, the parser tries to skip until the end of the line. However, if the line ends with a whitespace, the tokenizer merges the whitespace and the new line, and consumes the next line. For example, this code can cause vunit to fail detecting the module:

`timescale 1ns / 1 ns 

module my_tb();

[kraigher]

Should be fixed on master now.

[haggaie]

Works for me, thanks!