reset for axi_stream_master #422
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added reset output to use when the axi_stream_master is generating the reset. changed wait until idle construction to use a notify from the bus process so that we are sure all transactions (including the reset) have been handled. added checking of reset input on places where it is required so that a reset is handled properly in the master. added axi_stream_reset to vci. added reset input to axi_stream_slave.vhd. added basic test for reset functionality.
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I like the addition of the reset to the master, but i would keep the reset generation out of it. Instead add a new component. which generates resets. (e.g. with synchronous asynchronous assert). This way it keeps a nice separation of functionality. In most of the designs I know the reset comes from some other source and not the master itself.
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| notify_bus_process_done <= '1'; | ||
| wait until notify_bus_process_done = '1'; | ||
| notify_bus_process_done <= '0'; |
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Also, I'am not sure, why this is needed. waiting for tvalid = '0' and aclk should be sufficient.
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this was necessary to be able to issue a reset 'request' and follow it up with a wait_until_idle to wait for it to complete.
When just adding a areset_out_n = '1' there was a timing hole and the wait_until_idle would complete to early.
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@go2sh Has a point. It would be more modular if there was a separate reset generator VC and the axi stream just had reset as an input? What do you say @olafvandenberg? |
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Ok, I agree, sound likes a plan, I'll need some time for it though. |
replaced reset out / reset in, with single reset input. adapted testbench.
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Yes a to drive a reset is nothing special so an general io vc is probably smart. |
added reset output to use when the axi_stream_master is generating the reset.
changed wait until idle construction to use a notify from the bus process so that we are sure all transactions (including the reset) have been handled.
added checking of reset input on places where it is required so that a reset is handled properly in the master.
added axi_stream_reset to vci.
added reset input to axi_stream_slave.vhd.
added basic test for reset functionality.