Set black line-length to 120 characters

examples/verilog/verilog_ams/run.py

@@ -12,8 +12,6 @@
 VU = VUnit.from_argv()
 LIB = VU.add_library("lib")
 LIB.add_source_files(ROOT / "*.sv")
-LIB.add_source_files(ROOT / "*.vams").set_compile_option(
-    "modelsim.vlog_flags", ["-ams"]
-)
+LIB.add_source_files(ROOT / "*.vams").set_compile_option("modelsim.vlog_flags", ["-ams"])
 
 VU.main()

examples/vhdl/array/run.py

@@ -21,9 +21,7 @@
 
 SRC_PATH = Path(__file__).parent / "src"
 
-VU.add_library("lib").add_source_files(
-    [SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"]
-)
+VU.add_library("lib").add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"])
 
 VU.set_compile_option("ghdl.flags", ["-frelaxed"])
 VU.set_sim_option("ghdl.elab_flags", ["-frelaxed"])

examples/vhdl/axi_dma/run.py

@@ -24,8 +24,6 @@
 
 SRC_PATH = Path(__file__).parent / "src"
 
-VU.add_library("axi_dma_lib").add_source_files(
-    [SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"]
-)
+VU.add_library("axi_dma_lib").add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"])
 
 VU.main()

examples/vhdl/composite_generics/run.py

@@ -28,18 +28,12 @@ def encode(tb_cfg):
 
 TEST.add_config(
     name="VGA",
-    generics=dict(
-        encoded_tb_cfg=encode(
-            dict(image_width=640, image_height=480, dump_debug_data=False)
-        )
-    ),
+    generics=dict(encoded_tb_cfg=encode(dict(image_width=640, image_height=480, dump_debug_data=False))),
 )
 
 TEST.add_config(
     name="tiny",
-    generics=dict(
-        encoded_tb_cfg=encode(dict(image_width=4, image_height=3, dump_debug_data=True))
-    ),
+    generics=dict(encoded_tb_cfg=encode(dict(image_width=4, image_height=3, dump_debug_data=True))),
 )
 
 VU.main()

examples/vhdl/json4vhdl/run.py

@@ -35,8 +35,6 @@
 TB.get_tests("stringified*")[0].set_generic("tb_cfg", JSON_STR)
 TB.get_tests("b16encoded stringified*")[0].set_generic("tb_cfg", b16encode(JSON_STR))
 TB.get_tests("JSON file*")[0].set_generic("tb_cfg", JSON_FILE)
-TB.get_tests("b16encoded JSON file*")[0].set_generic(
-    "tb_cfg", b16encode(str(TEST_PATH / JSON_FILE))
-)
+TB.get_tests("b16encoded JSON file*")[0].set_generic("tb_cfg", b16encode(str(TEST_PATH / JSON_FILE)))
 
 VU.main()

examples/vhdl/run/run.py

@@ -20,8 +20,6 @@
 
 LIB = VU.add_library("lib")
 LIB.add_source_files(ROOT / "*.vhd")
-LIB.entity("tb_with_lower_level_control").scan_tests_from_file(
-    ROOT / "test_control.vhd"
-)
+LIB.entity("tb_with_lower_level_control").scan_tests_from_file(ROOT / "test_control.vhd")
 
 VU.main()

examples/vhdl/vivado/vivado_util.py

@@ -41,10 +41,7 @@ def compile_standard_libraries(vunit_obj, output_path):
     simulator_class = SIMULATOR_FACTORY.select_simulator()
 
     if not done_token.exists():
-        print(
-            "Compiling standard libraries into %s ..."
-            % str(Path(output_path).resolve())
-        )
+        print("Compiling standard libraries into %s ..." % str(Path(output_path).resolve()))
         simname = simulator_class.name
 
         # Vivado calls rivierapro for riviera
@@ -61,10 +58,7 @@ def compile_standard_libraries(vunit_obj, output_path):
         )
 
     else:
-        print(
-            "Standard libraries already exists in %s, skipping"
-            % str(Path(output_path).resolve())
-        )
+        print("Standard libraries already exists in %s, skipping" % str(Path(output_path).resolve()))
 
     for library_name in ["unisim", "unimacro", "unifast", "secureip", "xpm"]:
         path = str(Path(output_path) / library_name)
@@ -88,13 +82,8 @@ def add_project_ip(vunit_obj, project_file, output_path, vivado_path=None, clean
     compile_order_file = str(Path(output_path) / "compile_order.txt")
 
     if clean or not Path(compile_order_file).exists():
-        create_compile_order_file(
-            project_file, compile_order_file, vivado_path=vivado_path
-        )
+        create_compile_order_file(project_file, compile_order_file, vivado_path=vivado_path)
     else:
-        print(
-            "Vivado project Compile order already exists, re-using: %s"
-            % str(Path(compile_order_file).resolve())
-        )
+        print("Vivado project Compile order already exists, re-using: %s" % str(Path(compile_order_file).resolve()))
 
     return add_from_compile_order_file(vunit_obj, compile_order_file)

pyproject.toml

@@ -5,6 +5,9 @@ requires = [
 ]
 build-backend = "setuptools.build_meta"
 
+[tool.black]
+line-length = 120
+
 [tool.tox]
 legacy_tox_ini = """
 [tox]

setup.py

@@ -37,9 +37,7 @@ def find_all_files(directory, endings=None):
 DATA_FILES = []
 DATA_FILES += find_all_files("vunit", endings=[".tcl"])
 DATA_FILES += find_all_files(str(Path("vunit") / "vhdl"))
-DATA_FILES += find_all_files(
-    str(Path("vunit") / "verilog"), endings=[".v", ".sv", ".svh"]
-)
+DATA_FILES += find_all_files(str(Path("vunit") / "verilog"), endings=[".v", ".sv", ".svh"])
 DATA_FILES = [os.path.relpath(file_name, "vunit") for file_name in DATA_FILES]
 
 setup(

tests/acceptance/artificial/verilog/run.py

@@ -29,9 +29,7 @@ def configure_tb_with_parameter_config():
 
     tests[3].add_config(
         "cfg",
-        parameters=dict(
-            set_parameter="set-for-test", config_parameter="set-from-config"
-        ),
+        parameters=dict(set_parameter="set-for-test", config_parameter="set-from-config"),
     )
 
     def post_check(output_path):
@@ -40,9 +38,7 @@ def post_check(output_path):
 
     tests[4].add_config(
         "cfg",
-        parameters=dict(
-            set_parameter="set-from-config", config_parameter="set-from-config"
-        ),
+        parameters=dict(set_parameter="set-from-config", config_parameter="set-from-config"),
         post_check=post_check,
     )
 
@@ -58,7 +54,5 @@ def post_check(output_path):
 
 configure_tb_with_parameter_config()
 configure_tb_same_sim_all_pass(VU)
-LIB.module("tb_other_file_tests").scan_tests_from_file(
-    str(ROOT / "other_file_tests.sv")
-)
+LIB.module("tb_other_file_tests").scan_tests_from_file(str(ROOT / "other_file_tests.sv"))
 VU.main()

tests/acceptance/artificial/vhdl/run.py

@@ -69,20 +69,15 @@ def configure_tb_set_generic(ui):
     tb.set_generic("str_quote_val", 'a"b')
     str_long_num = 512
     tb.set_generic("str_long_num", str_long_num)
-    tb.set_generic(
-        "str_long_val", "".join(["0123456789abcdef" for x in range(str_long_num)])
-    )
+    tb.set_generic("str_long_val", "".join(["0123456789abcdef" for x in range(str_long_num)]))
 
 
 def configure_tb_assert_stop_level(ui):
     tb = ui.library("lib").entity("tb_assert_stop_level")
 
     for vhdl_assert_stop_level in ["warning", "error", "failure"]:
         for report_level in ["warning", "error", "failure"]:
-            test = tb.test(
-                "Report %s when VHDL assert stop level = %s"
-                % (report_level, vhdl_assert_stop_level)
-            )
+            test = tb.test("Report %s when VHDL assert stop level = %s" % (report_level, vhdl_assert_stop_level))
             test.set_sim_option("vhdl_assert_stop_level", vhdl_assert_stop_level)
 
 
@@ -92,7 +87,5 @@ def configure_tb_assert_stop_level(ui):
 configure_tb_assert_stop_level(VU)
 LIB.entity("tb_no_generic_override").set_generic("g_val", False)
 LIB.entity("tb_ieee_warning").test("pass").set_sim_option("disable_ieee_warnings", True)
-LIB.entity("tb_other_file_tests").scan_tests_from_file(
-    str(ROOT / "other_file_tests.vhd")
-)
+LIB.entity("tb_other_file_tests").scan_tests_from_file(str(ROOT / "other_file_tests.vhd"))
 VU.main()

tests/acceptance/test_artificial.py

@@ -89,27 +89,19 @@ def test_run_selected_tests_in_same_sim_test_bench_vhdl(self):
 
     @unittest.skipUnless(simulator_is("modelsim"), "Only modelsim supports verilog")
     def test_run_selected_tests_in_same_sim_test_bench_verilog(self):
-        self._test_run_selected_tests_in_same_sim_test_bench(
-            self.artificial_run_verilog
-        )
+        self._test_run_selected_tests_in_same_sim_test_bench(self.artificial_run_verilog)
 
     def _test_run_selected_tests_in_same_sim_test_bench(self, run_file):
         """
         Run selected "same_sim" test in isolation
         """
-        self.check(
-            run_file, exit_code=0, clean=True, args=["*same_sim_some_fail*Test 1*"]
-        )
+        self.check(run_file, exit_code=0, clean=True, args=["*same_sim_some_fail*Test 1*"])
         check_report(self.report_file, [("passed", "lib.tb_same_sim_some_fail.Test 1")])
 
-        self.check(
-            run_file, exit_code=1, clean=False, args=["*same_sim_some_fail*Test 2*"]
-        )
+        self.check(run_file, exit_code=1, clean=False, args=["*same_sim_some_fail*Test 2*"])
         check_report(self.report_file, [("failed", "lib.tb_same_sim_some_fail.Test 2")])
 
-        self.check(
-            run_file, exit_code=0, clean=False, args=["*same_sim_some_fail*Test 3*"]
-        )
+        self.check(run_file, exit_code=0, clean=False, args=["*same_sim_some_fail*Test 3*"])
         check_report(self.report_file, [("passed", "lib.tb_same_sim_some_fail.Test 3")])
 
         self.check(
@@ -181,9 +173,7 @@ def check(self, run_file, args=None, clean=True, exit_code=0):
 
     def test_exit_0_flag(self):
         self.check(self.artificial_run_vhdl, exit_code=1, args=["lib.tb_fail.all"])
-        self.check(
-            self.artificial_run_vhdl, exit_code=0, args=["--exit-0", "lib.tb_fail.all"]
-        )
+        self.check(self.artificial_run_vhdl, exit_code=0, args=["--exit-0", "lib.tb_fail.all"])
 
 
 EXPECTED_REPORT = (

tests/acceptance/test_external_run_scripts.py

@@ -155,9 +155,7 @@ def test_vhdl_composite_generics_example_project(self):
             ],
         )
 
-    @unittest.skipUnless(
-        simulator_is("ghdl"), "Support complex JSON strings as generic"
-    )
+    @unittest.skipUnless(simulator_is("ghdl"), "Support complex JSON strings as generic")
     def test_vhdl_json4vhdl_example_project(self):
         self.check(str(ROOT / "examples" / "vhdl" / "json4vhdl" / "run.py"))
 
@@ -171,9 +169,7 @@ def test_vhdl_axi_dma_example_project(self):
         self.check(str(ROOT / "examples" / "vhdl" / "axi_dma" / "run.py"))
 
     def test_vhdl_user_guide_example_project(self):
-        self.check(
-            str(ROOT / "examples" / "vhdl" / "user_guide" / "run.py"), exit_code=1
-        )
+        self.check(str(ROOT / "examples" / "vhdl" / "user_guide" / "run.py"), exit_code=1)
         check_report(
             self.report_file,
             [
@@ -185,9 +181,7 @@ def test_vhdl_user_guide_example_project(self):
 
     @unittest.skipUnless(simulator_supports_verilog(), "Verilog")
     def test_verilog_user_guide_example_project(self):
-        self.check(
-            str(ROOT / "examples" / "verilog" / "user_guide" / "run.py"), exit_code=1
-        )
+        self.check(str(ROOT / "examples" / "verilog" / "user_guide" / "run.py"), exit_code=1)
         check_report(
             self.report_file,
             [

tests/common.py

@@ -42,9 +42,7 @@ def check_report(report_file, tests=None):
 
     for status, name in tests:
         if report[name] != status:
-            raise AssertionError(
-                "Wrong status of %s got %s expected %s" % (name, report[name], status)
-            )
+            raise AssertionError("Wrong status of %s got %s expected %s" % (name, report[name], status))
 
     num_tests = int(root.attrib["tests"])
     assert num_tests == len(tests)
@@ -128,9 +126,7 @@ def new_function(*args, **kwargs):
     return new_function
 
 
-def get_vhdl_test_bench(
-    test_bench_name, tests=None, same_sim=False, test_attributes=None
-):
+def get_vhdl_test_bench(test_bench_name, tests=None, same_sim=False, test_attributes=None):
     """
     Create a valid VUnit test bench
 
@@ -190,9 +186,7 @@ def get_vhdl_test_bench(
     return contents
 
 
-def create_vhdl_test_bench_file(
-    test_bench_name, file_name, tests=None, same_sim=False, test_attributes=None
-):
+def create_vhdl_test_bench_file(test_bench_name, file_name, tests=None, same_sim=False, test_attributes=None):
     """
     Create a valid VUnit test bench and writes it to file_name
     """

tests/lint/test_license.py

@@ -22,10 +22,8 @@
 ROOT = Path(RSTR)
 
 RE_LICENSE_NOTICE = re.compile(
-    r"(?P<comment_start>#|--|//) This Source Code Form is subject to the terms of the Mozilla Public"
-    + "\n"
-    r"(?P=comment_start) License, v\. 2\.0\. If a copy of the MPL was not distributed with this file,"
-    + "\n"
+    r"(?P<comment_start>#|--|//) This Source Code Form is subject to the terms of the Mozilla Public" + "\n"
+    r"(?P=comment_start) License, v\. 2\.0\. If a copy of the MPL was not distributed with this file," + "\n"
     r"(?P=comment_start) You can obtain one at http://mozilla\.org/MPL/2\.0/\." + "\n"
     r"(?P=comment_start)" + "\n"
     r"(?P=comment_start) Copyright \(c\) (?P<first_year>20\d\d)(-(?P<last_year>20\d\d))?, "
@@ -70,14 +68,12 @@ def _check_license(self, code, file_name):
         self.assertEqual(
             int(match.group("first_year")),
             FIRST_YEAR,
-            "Expected copyright year range to start with %d in %s"
-            % (FIRST_YEAR, file_name),
+            "Expected copyright year range to start with %d in %s" % (FIRST_YEAR, file_name),
         )
         self.assertEqual(
             int(match.group("last_year")),
             LAST_YEAR,
-            "Expected copyright year range to end with %d in %s"
-            % (LAST_YEAR, file_name),
+            "Expected copyright year range to end with %d in %s" % (LAST_YEAR, file_name),
         )
 
     @staticmethod
@@ -97,9 +93,7 @@ def _check_no_trailing_whitespace(code, file_name):
             for _ in range(len(line) - len(sline)):
                 print("~", end="")
             print()
-            raise AssertionError(
-                "Line %i of %s contains trailing whitespace" % (idx + 1, file_name)
-            )
+            raise AssertionError("Line %i of %s contains trailing whitespace" % (idx + 1, file_name))
 
 
 def fix_license(file_name):