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drm/i915: enable HiZ Raw Stall Optimization #4

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merged 1 commit into from
Sep 17, 2014
Merged

drm/i915: enable HiZ Raw Stall Optimization #4

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2 changes: 2 additions & 0 deletions drivers/gpu/drm/i915/i915_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -711,6 +711,8 @@
#define ECO_GATING_CX_ONLY (1<<3)
#define ECO_FLIP_DONE (1<<0)

#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
#define CACHE_MODE_1 0x7004 /* IVB+ */
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)

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12 changes: 10 additions & 2 deletions drivers/gpu/drm/i915/i915_suspend.c
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Original file line number Diff line number Diff line change
Expand Up @@ -357,7 +357,10 @@ int i915_save_state(struct drm_device *dev)
intel_disable_gt_powersave(dev);

/* Cache mode state */
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
if (INTEL_INFO(dev)->gen >= 7)
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
else
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);

/* Memory Arbitration state */
dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
Expand Down Expand Up @@ -404,7 +407,12 @@ int i915_restore_state(struct drm_device *dev)
}

/* Cache mode state */
I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
if (INTEL_INFO(dev)->gen >= 7)
I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
0xffff0000);
else
I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
0xffff0000);

/* Memory arbitration state */
I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
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12 changes: 10 additions & 2 deletions drivers/gpu/drm/i915/intel_pm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3803,7 +3803,11 @@ static void haswell_init_clock_gating(struct drm_device *dev)

gen7_setup_fixed_func_scheduler(dev_priv);

/* WaDisable4x2SubspanOptimization */
/* enable HiZ Raw Stall Optimization */
I915_WRITE(CACHE_MODE_0_GEN7,
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));

/* WaDisable4x2SubspanOptimization:hsw */
I915_WRITE(CACHE_MODE_1,
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

Expand Down Expand Up @@ -3911,7 +3915,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)

gen7_setup_fixed_func_scheduler(dev_priv);

/* WaDisable4x2SubspanOptimization */
/* enable HiZ Raw Stall Optimization */
I915_WRITE(CACHE_MODE_0_GEN7,
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));

/* WaDisable4x2SubspanOptimization:ivb */
I915_WRITE(CACHE_MODE_1,
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

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