Skip to content
This repository was archived by the owner on Dec 22, 2021. It is now read-only.

Prefetch instructions #352

Closed
wants to merge 1 commit into from
Closed

Prefetch instructions #352

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions proposals/simd/BinarySIMD.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -249,3 +249,5 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
| `v128.store16_lane` | `TBD`| m:memarg, i:ImmLaneIdx8 |
| `v128.store32_lane` | `TBD`| m:memarg, i:ImmLaneIdx4 |
| `v128.store64_lane` | `TBD`| m:memarg, i:ImmLaneIdx2 |
| `prefetch.t` | `TBD`| - |
| `prefetch.nt` | `TBD`| - |
5 changes: 5 additions & 0 deletions proposals/simd/NewOpcodes.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -130,3 +130,8 @@
| i32x4.trunc_sat_f32x4_u | 0xf9 |
| f32x4.convert_i32x4_s | 0xfa |
| f32x4.convert_i32x4_u | 0xfb |

| Prefetch Op | opcode |
| ------------| ------ |
| prefetch.t | 0xfc |
| prefetch.nt | 0xfd |
10 changes: 10 additions & 0 deletions proposals/simd/SIMD.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1105,3 +1105,13 @@ def S.widen_low_T_u(a):
def S.widen_high_T_u(a):
return S.widen_high_T(Zext, a)
```

### Prefetch

* `prefetch.t(memarg)`
* `prefetch.nt(memarg)`

Prefetch memory location into lowest-level cache. Prefetch with temporal hint
(`prefetch.t`) should be used for data that will be used only once, and
prefetch with non-temporal (`prefetch.nt`) hint for data that will be reused
multiple times.