Update test runner to compare test output with expected test output #11
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rossberg
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Aug 18, 2015
Update test runner to compare test output with expected test output
alexcrichton
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Nov 18, 2019
This change adds a variable shuffle instruction to SIMD proposal. When indices are out of range, the result is specified as 0 for each lane. This matches hardware behavior on ARM and RISCV architectures. On x86_64 and MIPS, the hardware provides instructions that can select 0 when the high bit is set to 1 (x86_64) or any of the two high bits are set to 1 (MIPS). On these architectures, the backend is expected to emit a pair of instructions, saturating add (saturate(x + (128 - 16)) for x86_64) and permute, to emulate the proposed behavior. To distinguish variable shuffles with immediate shuffles, existing v8x16.shuffle instruction is renamed to v8x16.shuffle2_imm to be explicit about the fact that it shuffles two vectors with an immediate argument. This naming scheme allows for adding variants like v8x16.shuffle2 and v8x16.shuffle1_imm in the future. Fixes WebAssembly#68. Contributes to WebAssembly#24. Fixes WebAssembly#11.
alexcrichton
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Jul 28, 2020
Start a binary encoding document
dhil
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Mar 2, 2023
dhil
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Oct 20, 2023
Merge with WebAssembly/spec and WebAssembly/gc
dhil
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Apr 12, 2024
Squashed commit of the following: * Typed Continuations explainer document * Typed Continuations formal spec * Typed Continuations examples (Typed Continuations reference interpreter implementation to follow separately.) Co-authored-by: Daniel Hillerström <daniel.hillerstrom@ed.ac.uk> Co-authored-by: Andreas Rossberg <rossberg@chromium.org>
rossberg
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Nov 6, 2024
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