[AIE2P] Introduce AIE_VSHIFT gMIR opcode and instruction select

llvm/lib/Target/AIE/AIEBaseInstrInfo.h

@@ -137,6 +137,9 @@ struct AIEBaseInstrInfo : public TargetInstrInfo {
     llvm_unreachable(
         "Target didn't implement getGenericBroadcastVectorOpcode!");
   }
+  virtual unsigned getGenericVShiftOpcode() const {
+    llvm_unreachable("Target didn't implement getGenericVShiftOpcode!");
+  }
   /// Check whether Opc represents a lock instruction
   virtual bool isLock(unsigned Opc) const { return false; }
   /// Check whether this is a delayed scheduling barrier induced from

llvm/lib/Target/AIE/AIEInstrGISel.td

@@ -109,3 +109,11 @@ def G_AIE_UNPAD_VECTOR : AIEGenericInstruction {
   let InOperandList = (ins type1:$src);
   let hasSideEffects = false;
 }
+
+// Concatenate the src1 and src2 vectors, shift right
+// and extract the resulting lower 512-bit vector
+def G_AIE_VSHIFT : AIEGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2, type1:$shift_amt);
+  let hasSideEffects = false;
+}

llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp

@@ -1536,6 +1536,10 @@ unsigned AIE2PInstrInfo::getGenericBroadcastVectorOpcode() const {
   return AIE2P::G_AIE_BROADCAST_VECTOR;
 }
 
+unsigned AIE2PInstrInfo::getGenericVShiftOpcode() const {
+  return AIE2P::G_AIE_VSHIFT;
+}
+
 Register AIE2PInstrInfo::getSSStatusReg() const { return AIE2P::srSS0; }
 
 Register AIE2PInstrInfo::getMSStatusReg() const { return AIE2P::srMS0; }

llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.h

@@ -60,6 +60,7 @@ class AIE2PInstrInfo : public AIE2PGenInstrInfo {
   unsigned getGenericPadVectorOpcode() const override;
   unsigned getGenericUnpadVectorOpcode() const override;
   unsigned getGenericBroadcastVectorOpcode() const override;
+  unsigned getGenericVShiftOpcode() const override;
   bool isLock(unsigned Opc) const override;
   bool isDelayedSchedBarrier(const MachineInstr &MI) const override;
   bool isSchedBarrier(const MachineInstr &MI) const override;

llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td

@@ -960,3 +960,16 @@ def : Pat<(xor Ty:$src1, Ty:$src2),
 // DIVS
 def : Pat<(int_aie2p_divs eR31:$sd_in, eR:$src0, eR:$src1),
           (DIVS eR31:$sd_in, eR:$src0, eR:$src1)>;
+
+// VSHIFT
+def vshift_node : SDNode<"AIE2P::G_AIE_VSHIFT",
+                          SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<3>,
+                                              SDTCisSameAs<0,1>,
+                                              SDTCisSameAs<0,2>]>>;
+def : GINodeEquiv<G_AIE_VSHIFT, vshift_node>;
+
+
+foreach Ty = [v64i8, v32i16, v16i32, v8i64] in {
+def : Pat<(Ty (vshift_node VEC512:$src1, VEC512:$src2, (i32 eR:$shift))),
+          (VSHIFT VEC512:$src1, VEC512:$src2, eR:$shift)>;
+}

llvm/test/CodeGen/AIE/GlobalISel/inst-select-aie-vshift.mir

@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+#
+# RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=AIE2P
+
+---
+name:            vshift_v64i8
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; AIE2P-LABEL: name: vshift_v64i8
+    ; AIE2P: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 12
+    ; AIE2P-NEXT: [[DEF:%[0-9]+]]:vec512 = IMPLICIT_DEF
+    ; AIE2P-NEXT: [[VSHIFT:%[0-9]+]]:vec512 = VSHIFT [[DEF]], [[DEF]], [[MOV_RLC_imm11_pseudo]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit [[VSHIFT]]
+    %0:gprregbank(s32) = G_CONSTANT i32 12
+    %1:vregbank(<64 x s8>) = G_IMPLICIT_DEF
+    %2:vregbank(<64 x s8>) = G_AIE_VSHIFT %1, %1, %0(s32)
+    PseudoRET implicit $lr, implicit %2
+...
+---
+name:            vshift_v32i16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; AIE2P-LABEL: name: vshift_v32i16
+    ; AIE2P: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 12
+    ; AIE2P-NEXT: [[DEF:%[0-9]+]]:vec512 = IMPLICIT_DEF
+    ; AIE2P-NEXT: [[VSHIFT:%[0-9]+]]:vec512 = VSHIFT [[DEF]], [[DEF]], [[MOV_RLC_imm11_pseudo]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit [[VSHIFT]]
+    %0:gprregbank(s32) = G_CONSTANT i32 12
+    %1:vregbank(<32 x s16>) = G_IMPLICIT_DEF
+    %2:vregbank(<32 x s16>) = G_AIE_VSHIFT %1, %1, %0(s32)
+    PseudoRET implicit $lr, implicit %2
+...
+---
+name:            vshift_v16i32
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; AIE2P-LABEL: name: vshift_v16i32
+    ; AIE2P: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 12
+    ; AIE2P-NEXT: [[DEF:%[0-9]+]]:vec512 = IMPLICIT_DEF
+    ; AIE2P-NEXT: [[VSHIFT:%[0-9]+]]:vec512 = VSHIFT [[DEF]], [[DEF]], [[MOV_RLC_imm11_pseudo]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit [[VSHIFT]]
+    %0:gprregbank(s32) = G_CONSTANT i32 12
+    %1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
+    %2:vregbank(<16 x s32>) = G_AIE_VSHIFT %1, %1, %0(s32)
+    PseudoRET implicit $lr, implicit %2
+...
+---
+name:            vshift_v8i64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; AIE2P-LABEL: name: vshift_v8i64
+    ; AIE2P: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 12
+    ; AIE2P-NEXT: [[DEF:%[0-9]+]]:vec512 = IMPLICIT_DEF
+    ; AIE2P-NEXT: [[VSHIFT:%[0-9]+]]:vec512 = VSHIFT [[DEF]], [[DEF]], [[MOV_RLC_imm11_pseudo]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit [[VSHIFT]]
+    %0:gprregbank(s32) = G_CONSTANT i32 12
+    %1:vregbank(<8 x s64>) = G_IMPLICIT_DEF
+    %2:vregbank(<8 x s64>) = G_AIE_VSHIFT %1, %1, %0(s32)
+    PseudoRET implicit $lr, implicit %2
+...