[AIE2] Enhance VMOV_mv_w instr itinerary #190
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| [2,1], [NoBypass, MOV_Bypass]>, | ||
| InstrItinData<II_VMOV_W_WML_WML, [EmptyCycles<1>, SimpleCycle<W_WM_PORT>], | ||
| [2,1], [MOV_Bypass, MOV_Bypass]>, | ||
| // FIXME: II_VMOV_X always book both the vector and accumulator read and write ports. |
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Will you address that in a follow-up PR, or are there fundamental problems for VMOV_X?
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Working on a follow-up PR.
No there are no fundamental problems for VMOV_X
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Work done here is merged as part of #196 |
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Have also handled the Bypass & No_Bypass for WL reg type. Please review the newly added itinerary thoroughly.