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[AIE2P] Enable legalization of 4x128-bit G_CONCAT_VECTORS #283

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[AIE2P] Enable legalization of 4x128-bit G_CONCAT_VECTORS #283

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4 changes: 1 addition & 3 deletions llvm/lib/Target/AIE/AIELegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1162,8 +1162,7 @@ bool AIELegalizerHelper::legalizeG_SELECT(LegalizerHelper &Helper,
}

// We legalize concat vector of 2 inputs. So, anything above we need to split
// it. So far expect only 4 input. 1024bit vector from 4 256bit register and
// 2048 accumulator register from 4 512bit registers.
// it. So far expect only 4 input.
bool AIELegalizerHelper::legalizeG_CONCAT_VECTORS(LegalizerHelper &Helper,
MachineInstr &MI) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
Expand All @@ -1174,7 +1173,6 @@ bool AIELegalizerHelper::legalizeG_CONCAT_VECTORS(LegalizerHelper &Helper,
const LLT DstTy = MRI.getType(DstReg);
const LLT SrcTy = MRI.getType(SrcReg);
assert(DstTy.isVector() && SrcTy.isVector() && "Expected vector types");
assert(SrcTy.getSizeInBits() >= 256 && "Input vector size does not match!");
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Do we want to allow G_CONCAT_VECTORS of 4x64-bit? I don't think we select the resulting concats of 2x64-bit.

assert(MI.getNumOperands() == 5 && "Expected 4 inputs!");

const LLT DstVecEltTy = DstTy.getElementType();
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25 changes: 25 additions & 0 deletions llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-concat-vector.mir
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Expand Up @@ -85,3 +85,28 @@ body: |
PseudoRET implicit $lr, implicit %4
...

---
name: test_v16s32
registers:
legalized: false
body: |
bb.0.entry:
liveins: $wl0, $wl1, $wl2, $wl3
; CHECK-LABEL: name: test_v16s
; CHECK: liveins: $wl0, $wl1, $wl2, $wl3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF3:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[DEF2]](<4 x s32>), [[DEF3]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[CONCAT_VECTORS]](<8 x s32>), [[CONCAT_VECTORS1]](<8 x s32>)
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[CONCAT_VECTORS2]](<16 x s32>)
%0:_(<4 x s32>) = G_IMPLICIT_DEF
%1:_(<4 x s32>) = G_IMPLICIT_DEF
%2:_(<4 x s32>) = G_IMPLICIT_DEF
%3:_(<4 x s32>) = G_IMPLICIT_DEF
%4:_(<16 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>)
PseudoRET implicit $lr, implicit %4
...
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