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Small typo fixes (mostly in AIEOps.td) (#1761)
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@hunhoffe
hunhoffe authored Sep 16, 2024
1 parent 52f2b81 commit ce58da3
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54 changes: 27 additions & 27 deletions include/aie/Dialect/AIE/IR/AIEOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -79,13 +79,13 @@ def AIE_TileOp: AIE_Op<"tile", [

let summary = "Declare an AIE tile";
let description = [{
This operation creates an AIE tile in the AIE array. We specify what the column and the row of the tile.
This operation creates an AIE tile in the AIE array. We specify the column and the row of the tile.

A tile encompasses core module (CoreOp), memory module (MemOp), stream switch (SwitchboxOp),
memory buffer (BufferOp), and lock (LockOp).

A tile is a logical abstraction. We use a tile to establish an ownership of a hardware entity
to it.
A tile is a logical abstraction. We use a tile to establish ownership of a hardware entity.

Note that row 0 of the Tile array is different from other rows, since it models the shim interface between
the AIE array proper and the PL. The South-West/Lower Right most core exists in Tile(0,1)
}];
Expand Down Expand Up @@ -196,7 +196,7 @@ def AIE_ShimSwitchboxOp: AIE_Op<"shim_switchbox", [
6 Ports to North (Core Tile) 4 Ports from North (Core Tile)
4 Ports to West 4 Ports from West
4 Ports to East 4 Ports from East
6 Ports to South(DMA, NoC I/F, PL I/F) 8 Ports from South (DMA, NoC I/F, PL I/F)
6 Ports to South (DMA, NoC I/F, PL I/F) 8 Ports from South (DMA, NoC I/F, PL I/F)
2 Ports to FIFOs 2 Ports from FIFOs
1 Port for control packet for Shim register access
1 Port for response to access for Shim registers
Expand Down Expand Up @@ -385,7 +385,7 @@ def AIE_ConnectOp: AIE_Op<"connect", [ParentOneOf<["SwitchboxOp", "ShimMuxOp"]>
This operation represents a programmed circuit-switched connection in a stream switch.
It associates a source bundle and source channel with a destination bundle and a destination channel.
This operation must exist within an `aie.switchbox` or `aie.shim_switchbox` operation.
All of the `aie.connect` operations in a switchbox must have a different destinations.
All of the `aie.connect` operations in a switchbox must have different destinations.
All of the `aie.connect` operations must also have a destination which is different from all
of the `aie.masterset` operations in the same switchbox.

Expand Down Expand Up @@ -505,7 +505,7 @@ def AIE_MasterSetOp: AIE_Op<"masterset", [
);
let summary = "Packet switched input connection";
let description = [{
A Packet switched connection inside a switchbox.
A packet switched connection inside a switchbox.
This operation specifies the configuration for a master port.

Example:
Expand Down Expand Up @@ -569,7 +569,7 @@ def AIE_PacketRulesOp: AIE_Op<"packet_rules", [SingleBlockImplicitTerminator<"En
let summary = "Packet switched routing rules";
let description = [{
This operation defines packet-switched routing configuration for packets entering a switchbox.
It references a port of the containing swithcbox, which be unique among other packetRules
It references a port of the containing switchbox, which must be unique among other packetRules
operations and [aie.connect]($aieconnect-aieconnectop) operations in the containing switchbox.
It contains a region of up to 4 [aie.rule](#aierule-aiepacketruleop) operations.

Expand Down Expand Up @@ -681,7 +681,7 @@ def AIE_PacketSourceOp: AIE_Op<"packet_source", [HasParent<"PacketFlowOp">]> {
);
let summary = "A sourceport";
let description = [{
A object representing the destination of a packet-switched flow. This must exist
An object representing the destination of a packet-switched flow. This must exist
within an [aie.packet_flow](#aiepacketflow-aiepacketflowop) operation.

See [aie.packet_flow](#aiepacketflow-aiepacketflowop) for an example.
Expand Down Expand Up @@ -766,8 +766,8 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> {
1. the offset into the buffer;
2. the transfer length;
3. the sizes and strides for n-d tensor addressing (described below);
4. the "bd_id" with which to associate the buffer descriptor (most often left empty).
5. the number of zeros to pad before and after every dimension of an n-d tensor (described below);
4. the "bd_id" with which to associate the buffer descriptor (most often left empty);
5. the number of zeros to pad before and after every dimension of an n-d tensor (described below).

`offset`, `len`, `size`s and `stride`s are all denominated in element width; e.g., transferring the whole of
`memref<512xi32>` means `len == 512`, and also while transferring the whole of `memref<512xi16>`, `len == 512`.
Expand Down Expand Up @@ -824,7 +824,7 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> {
[<size_2, stride_2>, <size_1, stride_1>, <size_0, stride_0>]
```

...translates to an access pattern that can be epxressed like this:
...translates to an access pattern that can be expressed like this:

```
int *buffer; // i32
Expand Down Expand Up @@ -1249,9 +1249,9 @@ def AIE_LockOp: AIE_Op<"lock", [
def AIE_UseLockOp: AIE_Op<"use_lock", []> {
let summary = "acquire/release lock op";
let description = [{
This operation uses a lock. In AIE1, a lock can be acquired with a value,
This operation uses a lock. In AIE1, a lock can be acquired with a value
or released with a value. This should be understood as a "blocking"
operation. In AIE2, locks are counting semaphores without inherent
operation. In AIE2, locks are counting semaphores without an inherent
acquired/release characteristic. This lock must appear in a parent op where
the tile can be determined (A CoreOp, a ShimDMAOp, a MemOp, or a
MemTileDMAOp).
Expand Down Expand Up @@ -1590,7 +1590,7 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol]
let summary = "Create a circular buffer or channel between two tiles";
let description = [{
The `aie.objectFifo` operation creates a circular buffer established between a producer and one or
more consumers, which are `aie.tile` operations. The`aie.objectFifo` instantiates the given number of
more consumers, which are `aie.tile` operations. The `aie.objectFifo` instantiates the given number of
buffers (of given output type) and their locks in the Memory Module of the appropriate tile(s) after
lowering, based on tile-adjacency. These elements represent the conceptual depth of the `objectFifo` or,
more specifically, of its object pool.
Expand Down Expand Up @@ -1633,14 +1633,14 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol]
On AIE-ML devices, objectFifos can also apply data layout transformations by
using the DMAs n-dimensional address generation scheme. Two transformations
can be applied for an objectFifo: one on the producer side, given by a
`toStream` attribute, and one transformation on the consumer side, given by
a `fromStream` attribute. See the `DMABDOp` documentation for a description
of strides and sizes. The `toStream` and `fromStream` optional attributes
`dimensionsToStream` attribute, and one transformation on the consumer side, given by
a `dimensionsFromStream` attribute. See the `DMABDOp` documentation for a description
of strides and sizes. The `dimensionsToStream` and `dimensionsFromStream` optional attributes
are given directly following the producer or consumer tile declaration.
Different transformations can be specified for each consumer. See example
below.

Note that using data layout transformations will cause the DMA be used even
Note that using data layout transformations will cause DMAs to be used even
between adjacent tiles whose objectFifos would otherwise use shared memory.

Further note that data layout transforms always apply at a granularity of
Expand All @@ -1655,10 +1655,10 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol]
all even indices from the stream, followed by all odd indices:

```
aie.objectfifo @of4 (%tile12 toStream [<16, 1>, <16, 16>, <1,1>],
aie.objectfifo @of4 (%tile12 dimensionsToStream [<16, 1>, <16, 16>, <1,1>],
{
%tile13 fromStream [],
%tile23 fromStream [<2, 1>, <128, 2>]
%tile13 dimensionsFromStream [],
%tile23 dimensionsFromStream [<2, 1>, <128, 2>]
}, 2 : i32
) : !aie.objectfifo<memref<256xi32>>
```
Expand Down Expand Up @@ -1734,7 +1734,7 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol]
def AIE_ObjectFifoLinkOp: AIE_Op<"objectfifo.link", [HasParent<"DeviceOp">]> {
let summary = "Links two objectFifos through an intermediary tile's DMA";
let description = [{
The `aie.objectFifo.link` operation allows to mark two or more `objectFifos` as linked. This implies that the `objectFifos` form
The `aie.objectFifo.link` operation marks two or more `objectFifos` as linked. This implies that the `objectFifos` form
one dataflow movement which is split accross multiple `objectFifos`. Specifically, during the `objectFifo` lowering there will
be less memory elements generated at the link point (i.e., the shared tile of all `objectFifos` in the link) as the `objectFifos` can share.

Expand All @@ -1747,10 +1747,10 @@ def AIE_ObjectFifoLinkOp: AIE_Op<"objectfifo.link", [HasParent<"DeviceOp">]> {
aie.objectfifo.link [@of1] -> [@of2] ([] [])
```
This operation links two `objectFifos` which have tile `%t72` as a link point. The offset input arrays are not required as the full size of
the objects is transferred from @of1 to @of2.
the objects are transferred from @of1 to @of2.

To achieve a broadcast pattern through the link tile, the output `objectFifo` should have a list of all the consumers tiles.
To achieve a distribute pattern from the link tile, there should be multiple output `objectFifos` in the LinkOp. In this case,
To achieve a distribute pattern from the link tile, there should be multiple output `objectFifos` in the OjbectFifoLinkOp. In this case,
parts will be taken out of the input `objectFifo`'s buffers based on dst_offsets input array.
The join pattern is the exact inverse of the distribute one and uses the src_offsets input array instead.
}];
Expand All @@ -1777,15 +1777,15 @@ def AIE_ObjectFifoLinkOp: AIE_Op<"objectfifo.link", [HasParent<"DeviceOp">]> {
bool isDistribute() { return getFifoOuts().size() > 1; }
std::optional<mlir::Value> getOptionalSharedTile();
std::optional<int> getRepeatCount();
std::vector<int> getJoinTranferLengths();
std::vector<int> getDistributeTranferLengths();
std::vector<int> getJoinTransferLengths();
std::vector<int> getDistributeTransferLengths();
}];
}

def AIE_ObjectFifoRegisterExternalBuffersOp: AIE_Op<"objectfifo.register_external_buffers", [
HasParent<"DeviceOp">, TileElement, IsShimNOCTile
]> {
let summary = "Registers external buffers to given object fifo shim tile(s) to use in the associated shim DMA(s)";
let summary = "Registers external buffers to an objectFifo's shim tile(s) for use in the associated shim DMA(s)";
let description = [{
The `aie.objectfifo.register_external_buffers` operation is used to register one or multiple external buffers
to the shim tile(s) used in an `objectFifo` creation. During the `objectFifo` lowering pass, shim DMAs that are
Expand Down
17 changes: 9 additions & 8 deletions lib/Dialect/AIE/IR/AIEDialect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -483,8 +483,9 @@ LogicalResult ObjectFifoCreateOp::verify() {
}

if (getProducerTileOp().isShimTile() && !getDimensionsToStream().empty()) {
return emitError("`toStream` data layout transformations are not supported "
"on shim tile producers");
return emitError(
"`dimensionsToStream` data layout transformations are not supported "
"on shim tile producers");
}

if (getViaSharedMem().has_value()) {
Expand Down Expand Up @@ -514,7 +515,7 @@ ParseResult parseObjectFifoProducerTile(OpAsmParser &parser,
std::vector<BDDimLayoutAttr> emptyDims = {};
if (parser.parseOperand(operand))
return failure();
if (succeeded(parser.parseOptionalKeyword("toStream"))) {
if (succeeded(parser.parseOptionalKeyword("dimensionsToStream"))) {
if (parser.parseCustomAttributeWithFallback<BDDimLayoutArrayAttr>(
dimensions)) {
return failure();
Expand All @@ -531,7 +532,7 @@ void printObjectFifoProducerTile(OpAsmPrinter &printer, Operation *op,
BDDimLayoutArrayAttr dimensions) {
printer << operand;
if (!dimensions.empty()) {
printer << " toStream ";
printer << " dimensionsToStream ";
printer.printStrippedAttrOrType(dimensions);
}
}
Expand All @@ -553,7 +554,7 @@ ParseResult parseObjectFifoConsumerTiles(
BDDimLayoutArrayAttr dimAttr =
BDDimLayoutArrayAttr::get(parser.getContext(), {});

if (succeeded(parser.parseOptionalKeyword("fromStream"))) {
if (succeeded(parser.parseOptionalKeyword("dimensionsFromStream"))) {
// If specified, parse actual data layout transform dimensions
if (parser.parseCustomAttributeWithFallback<BDDimLayoutArrayAttr>(
dimAttr)) {
Expand All @@ -580,7 +581,7 @@ void printObjectFifoConsumerTiles(OpAsmPrinter &printer, Operation *op,
printer << tile;
if (dimsPerTileAttr && tileIdx < dimsPerTileAttr.size() &&
dimsPerTileAttr[tileIdx] && !dimsPerTileAttr[tileIdx].empty()) {
printer << " fromStream ";
printer << " dimensionsFromStream ";
printer.printStrippedAttrOrType(dimsPerTileAttr[tileIdx]);
}
if (tileIdx < tiles.size() - 1) {
Expand Down Expand Up @@ -718,7 +719,7 @@ std::vector<ObjectFifoCreateOp> ObjectFifoLinkOp::getOutputObjectFifos() {
return outputObjFifos;
}

std::vector<int> ObjectFifoLinkOp::getJoinTranferLengths() {
std::vector<int> ObjectFifoLinkOp::getJoinTransferLengths() {
std::vector<int> lengths;
if (isJoin()) {
auto fifoOut =
Expand All @@ -738,7 +739,7 @@ std::vector<int> ObjectFifoLinkOp::getJoinTranferLengths() {
return lengths;
}

std::vector<int> ObjectFifoLinkOp::getDistributeTranferLengths() {
std::vector<int> ObjectFifoLinkOp::getDistributeTransferLengths() {
std::vector<int> lengths;
if (isDistribute()) {
auto fifoIn =
Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -741,7 +741,7 @@ struct AIEObjectFifoStatefulTransformPass
i++;
}
extraOffset = *getConstantIntValue(srcOffsets[i]);
lenOut = linkOp->getJoinTranferLengths()[i];
lenOut = linkOp->getJoinTransferLengths()[i];
}
} else if (linkOp->isDistribute()) {
// compute offset and length
Expand All @@ -757,7 +757,7 @@ struct AIEObjectFifoStatefulTransformPass
i++;
}
extraOffset = *getConstantIntValue(dstOffsets[i]);
lenOut = linkOp->getDistributeTranferLengths()[i];
lenOut = linkOp->getDistributeTransferLengths()[i];
}
} else {
if (target != op) {
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/AIEX/IR/AIEXDialect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -205,7 +205,7 @@ verifyStridesWraps(mlir::Operation *forOp, mlir::MemRefType referencedBufType,
}

for (int i = 0; i < 4; i++) {
// strides[0] == 1 is ok iff the tranfer size is a multiple of
// strides[0] == 1 is ok iff the transfer size is a multiple of
// addressGranularity, which is checked below
if (i == 0 && inputStrides[i] == 1)
continue;
Expand Down
10 changes: 5 additions & 5 deletions test/dialect/AIE/roundtrip.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@

// RUN: aie-opt --split-input-file %s | FileCheck %s

// aie.objectfifo.link with multiple consumers with toStream
// aie.objectfifo.link with multiple consumers with dimensionsToStream
// CHECK: aie.device
// CHECK: %[[TILE_0_2:.+]] = aie.tile(0, 2)
// CHECK: %[[TILE_0_3:.+]] = aie.tile(0, 3)
Expand All @@ -19,8 +19,8 @@
// CHECK: %[[TILE_0_0:.+]] = aie.tile(0, 0)
// CHECK: %[[TILE_0_1:.+]] = aie.tile(0, 1)
// CHECK: aie.objectfifo @obj1(%[[TILE_0_0]], {%[[TILE_0_1]]}, 4 : i32) : !aie.objectfifo<memref<2048xi32, 1>>
// CHECK: aie.objectfifo @obj2(%[[TILE_0_1]] toStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%[[TILE_0_2]], %[[TILE_0_3]]}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
// CHECK: aie.objectfifo @obj3(%[[TILE_0_1]] toStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%[[TILE_1_2]], %[[TILE_1_3]]}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
// CHECK: aie.objectfifo @obj2(%[[TILE_0_1]] dimensionsToStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%[[TILE_0_2]], %[[TILE_0_3]]}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
// CHECK: aie.objectfifo @obj3(%[[TILE_0_1]] dimensionsToStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%[[TILE_1_2]], %[[TILE_1_3]]}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
// CHECK: aie.objectfifo.link [@obj1] -> [@obj2, @obj3]([] [0, 1024])
aie.device(npu1_4col) {
memref.global "public" @out0 : memref<16xi32>
Expand All @@ -31,7 +31,7 @@ aie.device(npu1_4col) {
%tile_0_0 = aie.tile(0, 0)
%tile_0_1 = aie.tile(0, 1)
aie.objectfifo @obj1(%tile_0_0, {%tile_0_1}, 4 : i32) : !aie.objectfifo<memref<2048xi32, 1>>
aie.objectfifo @obj2(%tile_0_1 toStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%tile_0_2, %tile_0_3}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
aie.objectfifo @obj3(%tile_0_1 toStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%tile_1_2, %tile_1_3}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
aie.objectfifo @obj2(%tile_0_1 dimensionsToStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%tile_0_2, %tile_0_3}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
aie.objectfifo @obj3(%tile_0_1 dimensionsToStream [<size = 8, stride = 4>, <size = 32, stride = 32>, <size = 4, stride = 1>], {%tile_1_2, %tile_1_3}, 4 : i32) : !aie.objectfifo<memref<1024xi32, 1>>
aie.objectfifo.link [@obj1] -> [@obj2, @obj3]([] [0, 1024])
}
4 changes: 2 additions & 2 deletions test/objectFifo-register-process/nd_dma_test_aie2.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
// CHECK-LABEL: aie.device(xcve2302) {
// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2)
// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3)
// CHECK: aie.objectfifo @objfifo(%[[VAL_0]] toStream [<size = 1, stride = 2>], {%[[VAL_1]] fromStream [<size = 3, stride = 4>]}, 4 : i32) : !aie.objectfifo<memref<16xi32>>
// CHECK: aie.objectfifo @objfifo(%[[VAL_0]] dimensionsToStream [<size = 1, stride = 2>], {%[[VAL_1]] dimensionsFromStream [<size = 3, stride = 4>]}, 4 : i32) : !aie.objectfifo<memref<16xi32>>
// CHECK: %[[VAL_2:.*]] = arith.constant dense<1> : tensor<1xi32>
// CHECK: %[[VAL_3:.*]] = arith.constant dense<1> : tensor<1xi32>
// CHECK: %[[VAL_4:.*]] = arith.constant 10 : index
Expand All @@ -41,7 +41,7 @@ module @registerPatterns {
%tile12 = aie.tile(1, 2)
%tile13 = aie.tile(1, 3)

aie.objectfifo @objfifo (%tile12 toStream [<size = 1, stride = 2>], {%tile13 fromStream [<size = 3, stride = 4>]}, 4 : i32) : !aie.objectfifo<memref<16xi32>>
aie.objectfifo @objfifo (%tile12 dimensionsToStream [<size = 1, stride = 2>], {%tile13 dimensionsFromStream [<size = 3, stride = 4>]}, 4 : i32) : !aie.objectfifo<memref<16xi32>>

%acquirePattern = arith.constant dense<[1]> : tensor<1xi32>
%releasePattern = arith.constant dense<[1]> : tensor<1xi32>
Expand Down
8 changes: 4 additions & 4 deletions test/objectFifo-stateful-transform/nd_dma_base_AIE2.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -131,12 +131,12 @@ module @ndDMAObjFifoAIE2 {

// Even if an objectFifo could be implemented in shared memory, as with
// this case between two adjacent tiles, we need to use DMAs if a data
// layout transformation with toStream and fromStream was specified.
aie.objectfifo @of0 (%tile12 toStream [<size = 16, stride = 1>, <size = 16, stride = 16>, <size = 1, stride = 1>], // transpose
{%tile13 fromStream [<size = 1, stride = 1>]},
// layout transformation with dimensionsToStream and dimensionsFromStream was specified.
aie.objectfifo @of0 (%tile12 dimensionsToStream [<size = 16, stride = 1>, <size = 16, stride = 16>, <size = 1, stride = 1>], // transpose
{%tile13 dimensionsFromStream [<size = 1, stride = 1>]},
4 : i32) : !aie.objectfifo<memref<256xi32>>

aie.objectfifo @of1 (%tile12 toStream [<size = 128, stride = 2>], {%tile33},
aie.objectfifo @of1 (%tile12 dimensionsToStream [<size = 128, stride = 2>], {%tile33},
2 : i32) : !aie.objectfifo<memref<256xi32>>
}
}
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