Switch to using transaction binary flow with no control packet #1517
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fifield
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May 29, 2024
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Requires this xdna-driver (or newer) |
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seems to be resolved |
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Coverage ReportCreated: 2024-06-07 21:05Click here for information about interpreting this report.
Generated by llvm-cov -- llvm version 14.0.0 |
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fifield
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Jun 6, 2024
Rename npu.shimtile_push_queue to npu.push_queue, remove metadata operand. Add direction, channel, column and row operands. Rename npu.writebd_shimtile to npu.writebd, remove column_num operand, add row operand. Make npu.write32 column and row operands optional. Before Xilinx#1517 this operation mapped to a firmware operation that interprets the address operand as a tile relative offset, then under the head uses (row, column, offset) to compute the write32 address. For backwards compatablity, if row and column are present, this behavior is preserved by aie-translate --aie-npu-instgen. Otherwise, the address operand is used without modification as the write32 address.
fifield
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Jun 6, 2024
Rename npu.shimtile_push_queue to npu.push_queue, remove metadata operand. Add direction, channel, column and row operands. Rename npu.writebd_shimtile to npu.writebd, remove column_num operand, add row operand. Make npu.write32 column and row operands optional. Before Xilinx#1517 this operation mapped to a firmware operation that interprets the address operand as a tile relative offset, then under the head uses (row, column, offset) to compute the write32 address. For backwards compatablity, if row and column are present, this behavior is preserved by aie-translate --aie-npu-instgen. Otherwise, the address operand is used without modification as the write32 address.
fifield
added a commit
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Jun 6, 2024
Rename npu.shimtile_push_queue to npu.push_queue, remove metadata operand. Add direction, channel, column and row operands. Rename npu.writebd_shimtile to npu.writebd, remove column_num operand, add row operand. Make npu.write32 column and row operands optional. Before Xilinx#1517 this operation mapped to a firmware operation that interprets the address operand as a tile relative offset, then under the head uses (row, column, offset) to compute the write32 address. For backwards compatablity, if row and column are present, this behavior is preserved by aie-translate --aie-npu-instgen. Otherwise, the address operand is used without modification as the write32 address.
fifield
added a commit
to fifield/mlir-aie
that referenced
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Jun 6, 2024
Rename npu.shimtile_push_queue to npu.push_queue, remove metadata operand. Add direction, channel, column and row operands. Rename npu.writebd_shimtile to npu.writebd, remove column_num operand, add row operand. Make npu.write32 column and row operands optional. Before Xilinx#1517 this operation mapped to a firmware operation that interprets the address operand as a tile relative offset, then under the hood uses (row, column, offset) to compute the write32 address. For backwards compatablity, if row and column are present, this behavior is preserved by aie-translate --aie-npu-instgen. Otherwise, the address operand is used without modification as the write32 address.
fifield
added a commit
to fifield/mlir-aie
that referenced
this pull request
Jun 6, 2024
Rename npu.shimtile_push_queue to npu.push_queue, remove metadata operand. Add direction, channel, column and row operands. Rename npu.writebd_shimtile to npu.writebd, remove column_num operand, add row operand. Make npu.write32 column and row operands optional. Before Xilinx#1517 this operation mapped to a firmware operation that interprets the address operand as a tile relative offset, then under the hood uses (row, column, offset) to compute the write32 address. For backwards compatibility, if row and column are present, this behavior is preserved by aie-translate --aie-npu-instgen. Otherwise, the address operand is used without modification as the write32 address.
jgmelber
approved these changes
Jun 10, 2024
|
@jgmelber I believe we need to update the version in |
Fixed in #1546 |
nirvedhmeshram
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Jun 13, 2024
This PR makes the required changes to switch to executing kernels with transaction binary flow with no control packets. This is done by simply updating the mlir-aie wheel to latest so that this PR is contained in it, Xilinx/mlir-aie#1517
fifield
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Jun 14, 2024
fifield
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Jun 14, 2024
* bump mlir-aie, llvm * update tests for Xilinx/mlir-aie#1517 * Apply suggestions from code review Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> * update pipelines to use one shot bufferize * bump mlir-aie * update xrt backend * update test * update for Xilinx/mlir-aie#1540 * Apply suggestions from code review Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> * update for write32 changes * update for write32 change part 2 * bump mlir-aie * fixup --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
This was referenced Jun 14, 2024
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Requires this xdna-driver (or newer)