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AIRRtToNpuPass SHIM DMA BD optimization #550

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merged 4 commits into from
Apr 25, 2024
Merged

AIRRtToNpuPass SHIM DMA BD optimization #550

merged 4 commits into from
Apr 25, 2024

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erwei-xilinx
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  • When tiling any wrap>1023 into two wraps, make the largest int factor the outer wrap, so that the new stride is smaller and less likely to go beyond 1M.
  • Code quality.
  • Avoid using SymbolTable::getSymbolUses method, which turns out to be quite slow with big IRs.

@erwei-xilinx erwei-xilinx requested a review from newling April 25, 2024 01:07
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newling approved these changes Apr 25, 2024
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Thanks!

@erwei-xilinx erwei-xilinx merged commit 4faaa09 into Xilinx:main Apr 25, 2024
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@erwei-xilinx erwei-xilinx deleted the improve_aiex_npu_dma_gemm_size_limit branch April 25, 2024 16:08
@erwei-xilinx erwei-xilinx mentioned this pull request Apr 25, 2024
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@newling newling newling approved these changes

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@erwei-xilinx @newling