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ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. #224

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roby2014 opened this issue Jan 24, 2023 · 0 comments

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@roby2014
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roby2014 commented Jan 24, 2023

Hello! Im trying to compile this project: iob-soc/tree/no-loops which uses picorv32.
However, the place & route is crashing because of:
ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.

git clone https://github.com/roby2014/iob-soc
cd iob-soc
git checkout no-loops
make fpga-build BOARD=COLORLIGHT_5A-75E REVISION=8.0 

From the log file, those are the last lines:

Info:    remaining fanin includes OFX (net system.cpu.picorv32_core.latched_is_lh_LUT4_D_1_Z_LUT4_D_Z_CCU2C_S1_COUT_CCU2C_COUT_S0_LUT4_B_Z_PFUMX_ALUT_Z[7])
Info:         driver = system.cpu.picorv32_core.latched_is_lh_LUT4_D_1_Z_LUT4_D_Z_CCU2C_S1_COUT_CCU2C_COUT_S1_LUT4_B_1.OFX
Info:         user: system.cpu.picorv32_core.reg_out_TRELLIS_FF_Q_24.M
Info:    remaining fanin includes OFX (net system.cpu.picorv32_core.mem_wstrb_TRELLIS_FF_Q_1_DI)
Info:         driver = system.cpu.picorv32_core.mem_wstrb_TRELLIS_FF_Q_1_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:         user: system.cpu.picorv32_core.mem_wstrb_TRELLIS_FF_Q_1.M
ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
2 warnings, 1 error

I suppose the error comes from picorv32_core.mem_wstrb.
How could I fix this issue?

@roby2014 roby2014 changed the title RAM block being instantiated as individual flip-flops timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. Jan 24, 2023
@roby2014 roby2014 changed the title timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. Jan 24, 2023
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