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@YosysHQ

Yosys Headquarters

Yosys Open SYnthesis Suite

YosysHQ - Open Source EDA

OSS CAD Suite: the one-stop shop for our tools

If you want to use our EDA tools, the easiest way is to install the binary release OSS CAD suite, which contains all required dependencies and related tools. Find the documentation here. We also have an OSS CAD Suite github action for using the tools in a github CI workflow.

Tabby CAD Suite is a commercial extension of OSS CAD Suite available from YosysHQ GmbH that additionally includes the Verific frontend for industry-grade SystemVerilog and VHDL support, formal verification with SVA, and formal apps.

Our Projects

Front-ends for applications built on top of Yosys:

  • sby: formal property checking
  • mcy: mutation coverage
  • eqy: equivalence checking

Other notable projects:

  • riscv-formal: formally check compliance with the RISC-V specification
  • picorv32: A Size-Optimized RISC-V CPU
  • nerv: A very simple educational RISC-V CPU for demonstrating riscv-formal

Community

Support us

Like what we do? Please consider either buying a license for the Tabby CAD Suite or becoming a sponsor.

Pinned Loading

  1. yosys yosys Public

    Yosys Open SYnthesis Suite

    C++ 3.8k 953

  2. nextpnr nextpnr Public

    nextpnr portable FPGA place and route tool

    C++ 1.4k 258

  3. sby sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    Python 455 81

  4. oss-cad-suite-build oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    Shell 1.1k 91

Repositories

Showing 10 of 41 repositories
  • nextpnr Public

    nextpnr portable FPGA place and route tool

    YosysHQ/nextpnr’s past year of commit activity
    C++ 1,442 ISC 258 106 (1 issue needs help) 11 Updated May 29, 2025
  • yosys Public

    Yosys Open SYnthesis Suite

    YosysHQ/yosys’s past year of commit activity
    C++ 3,839 ISC 953 484 122 Updated May 29, 2025
  • oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    YosysHQ/oss-cad-suite-build’s past year of commit activity
    Shell 1,059 ISC 91 58 4 Updated May 29, 2025
  • prjpeppercorn Public

    Project Peppercorn - GateMate FPGA Bitstream Documentation

    YosysHQ/prjpeppercorn’s past year of commit activity
    Python 21 ISC 2 0 0 Updated May 27, 2025
  • riscv-formal Public

    RISC-V Formal Verification Framework

    YosysHQ/riscv-formal’s past year of commit activity
    Verilog 139 ISC 30 6 5 Updated May 27, 2025
  • apicula Public

    Project Apicula 🐝: bitstream documentation for Gowin FPGAs

    YosysHQ/apicula’s past year of commit activity
    Verilog 554 MIT 74 13 4 Updated May 26, 2025
  • prjpeppercorn-test-cases Public

    Project Peppercorn GateMate Test Cases

    YosysHQ/prjpeppercorn-test-cases’s past year of commit activity
    Verilog 8 ISC 4 0 0 Updated May 26, 2025
  • sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    YosysHQ/sby’s past year of commit activity
    Python 455 81 40 10 Updated May 14, 2025
  • eqy Public

    Equivalence checking with Yosys

    YosysHQ/eqy’s past year of commit activity
    Python 43 7 13 0 Updated May 6, 2025
  • mcy Public

    Mutation Cover with Yosys (MCY)

    YosysHQ/mcy’s past year of commit activity
    C++ 82 ISC 11 2 0 Updated May 6, 2025

Most used topics

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