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@YosysHQ

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  1. YosysHQ/nextpnr Public

    nextpnr portable FPGA place and route tool

    C++ 1.5k 268

  2. YosysHQ/yosys Public

    Yosys Open SYnthesis Suite

    C++ 3.9k 972

  3. YosysHQ/prjtrellis Public

    Documenting the Lattice ECP5 bit-stream format.

    Python 420 91

  4. prjoxide Public

    Documenting Lattice's 28nm FPGA parts

    Python 143 14

  5. TrellisBoard Public

    Ultimate ECP5 development board

    ANTLR 111 11

  6. meowality Public

    Python 16 1

382 contributions in the last year

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Activity overview

Contributed to YosysHQ/nextpnr, ChipFlow/chipflow-lib, ChipFlow/chipflow-examples and 25 other repositories
Loading A graph representing gatecat's contributions from July 07, 2024 to July 12, 2025. The contributions are 46% commits, 35% code review, 15% pull requests, 4% issues.

Contribution activity

July 2025

Created 1 repository
  • gatecat/mame C++
    This contribution was made on Jul 8

Created a pull request in ChipFlow/chipflow-examples that received 3 comments

Opened 2 other pull requests in 2 repositories
Reviewed 3 pull requests in 2 repositories
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