Skip to content

Issues: YosysHQ/yosys

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

Rename techmap feature-request
#4759 opened Nov 19, 2024 by widlarizer
Usable gtest feature-request
#4758 opened Nov 19, 2024 by widlarizer
Internal Yosys nodes not removed pending-verification This issue is pending verification and/or reproduction
#4738 opened Nov 13, 2024 by ashkanr65
Module parameters are not affected by setundef pass pending-verification This issue is pending verification and/or reproduction
#4732 opened Nov 12, 2024 by kamilrakoczy
muxcover generates x states pending-verification This issue is pending verification and/or reproduction
#4722 opened Nov 8, 2024 by miradarya
Yosys does not accept module port lists with .port_identifier pending-verification This issue is pending verification and/or reproduction
#4708 opened Nov 5, 2024 by ldoolitt
Yosys seems to be inconsistent with the original design. pending-verification This issue is pending verification and/or reproduction
#4695 opened Oct 31, 2024 by smlz123
Segfault in XAIGER bug
#4689 opened Oct 29, 2024 by Periodic1911
Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v" pending-verification This issue is pending verification and/or reproduction
#4687 opened Oct 28, 2024 by 1353369570
'synth_intel' command,synthesis result is wrong pending-verification This issue is pending verification and/or reproduction
#4673 opened Oct 17, 2024 by CL-liao
Verilog globals appended to modules instead of prepended pending-verification This issue is pending verification and/or reproduction
#4653 opened Oct 10, 2024 by jmi2k
FSM pass equivalence bug pending-verification This issue is pending verification and/or reproduction
#4651 opened Oct 10, 2024 by joonho3020
sta command hangs on some designs pending-verification This issue is pending verification and/or reproduction
#4648 opened Oct 9, 2024 by lukbau
Co-simulation fails for $fa cell pending-verification This issue is pending verification and/or reproduction
#4638 opened Oct 7, 2024 by RCoeurjoly
tee -q -o <bad-path> fails silently pending-verification This issue is pending verification and/or reproduction
#4636 opened Oct 7, 2024 by povik
log_deprecated feature-request
#4623 opened Oct 1, 2024 by widlarizer
ProTip! Type g i on any issue or pull request to go back to the issue listing page.