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464 Open 1,321 Closed
464 Open 1,321 Closed
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Issues list

INIT of LUT1 must be 2 bit ? pending-verification This issue is pending verification and/or reproduction
#4826 opened Dec 23, 2024 by lehaifeng000
1
Built yosys.wasm is too large pending-verification This issue is pending verification and/or reproduction
#4822 opened Dec 18, 2024 by LSTM-Kirigaya
1
Add an optional yosys start script feature-request
#4820 opened Dec 16, 2024 by widlarizer
1
synth_xilinx error in simple demo bug
#4816 opened Dec 13, 2024 by lehaifeng000
3
Deviation Between Yosys RTLIL EBNF Docs and RTLIL Lex/Yacc Frontend pending-verification This issue is pending verification and/or reproduction
#4811 opened Dec 10, 2024 by ThePerfectComputer
5
Synthesis with -nowidelut gives drastically better results pending-verification This issue is pending verification and/or reproduction
#4798 opened Dec 5, 2024 by t-wallet
1
techmap should warn when CONSTMSK/CONSTVAL are used with a nonexistent port feature-request
#4795 opened Dec 3, 2024 by Ravenslofty
Preservation of signedness flag on attribute values inconsistent pending-verification This issue is pending verification and/or reproduction
#4793 opened Dec 2, 2024 by povik
read_verilog gives multiple drivers to variables initialized both in declaration and initial pending-verification This issue is pending verification and/or reproduction
#4792 opened Dec 2, 2024 by widlarizer
cxxrtl output port changes value after back to back .step() bug cxxrtl
#4786 opened Nov 29, 2024 by rroohhh
4
read_verilog: array of instances parsing assertion failure pending-verification This issue is pending verification and/or reproduction
#4785 opened Nov 29, 2024 by Muxianesty
1
Verilog: Mixing integer and real values causes error pending-verification This issue is pending verification and/or reproduction
#4780 opened Nov 28, 2024 by flafflar
2
Docs issues for offline pdf builds pending-verification This issue is pending verification and/or reproduction
#4777 opened Nov 28, 2024 by KrystalDelusion
Error: Abc_CommandAbc9If(): Mapping of GIA has failed. pending-verification This issue is pending verification and/or reproduction
#4766 opened Nov 24, 2024 by spth
1
Measure global_id_index_ construction overhead feature-request
#4761 opened Nov 20, 2024 by widlarizer
Rename techmap feature-request
#4759 opened Nov 19, 2024 by widlarizer
@povik
Usable gtest feature-request
#4758 opened Nov 19, 2024 by widlarizer
@widlarizer
write_verilog does not replace bwmux instances bug
#4751 opened Nov 15, 2024 by 7FM
1
@povik
3
Internal Yosys nodes not removed pending-verification This issue is pending verification and/or reproduction
#4738 opened Nov 13, 2024 by ashkanr65
9
Module parameters are not affected by setundef pass pending-verification This issue is pending verification and/or reproduction
#4732 opened Nov 12, 2024 by kamilrakoczy
1
muxcover generates x states pending-verification This issue is pending verification and/or reproduction
#4722 opened Nov 8, 2024 by miradarya
Reduce compiler warnings when building yosys feature-request
#4713 opened Nov 6, 2024 by ldoolitt
1
Yosys does not accept module port lists with .port_identifier pending-verification This issue is pending verification and/or reproduction
#4708 opened Nov 5, 2024 by ldoolitt
1
Yosys seems to be inconsistent with the original design. pending-verification This issue is pending verification and/or reproduction
#4695 opened Oct 31, 2024 by smlz123
3
segfault in proc_dlatch when latch is driven by conflicting drivers bug
#4692 opened Oct 30, 2024 by gadfort
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