-
Notifications
You must be signed in to change notification settings - Fork 894
Issues: YosysHQ/yosys
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Measure global_id_index_ construction overhead
feature-request
#4761
opened Nov 20, 2024 by
widlarizer
Internal Yosys nodes not removed
pending-verification
This issue is pending verification and/or reproduction
#4738
opened Nov 13, 2024 by
ashkanr65
Module parameters are not affected by setundef pass
pending-verification
This issue is pending verification and/or reproduction
#4732
opened Nov 12, 2024 by
kamilrakoczy
muxcover generates x states
pending-verification
This issue is pending verification and/or reproduction
#4722
opened Nov 8, 2024 by
miradarya
Yosys does not accept module port lists with .port_identifier
pending-verification
This issue is pending verification and/or reproduction
#4708
opened Nov 5, 2024 by
ldoolitt
Yosys seems to be inconsistent with the original design.
pending-verification
This issue is pending verification and/or reproduction
#4695
opened Oct 31, 2024 by
smlz123
segfault in proc_dlatch when latch is driven by conflicting drivers
bug
#4692
opened Oct 30, 2024 by
gadfort
Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v"
pending-verification
This issue is pending verification and/or reproduction
#4687
opened Oct 28, 2024 by
1353369570
'synth_intel' command,synthesis result is wrong
pending-verification
This issue is pending verification and/or reproduction
#4673
opened Oct 17, 2024 by
CL-liao
Assert
flow.wire_comb_defs[it].size() == 1
in write_cxxrtl
bug
cxxrtl
#4664
opened Oct 14, 2024 by
rroohhh
Verilog globals appended to modules instead of prepended
pending-verification
This issue is pending verification and/or reproduction
#4653
opened Oct 10, 2024 by
jmi2k
FSM pass equivalence bug
pending-verification
This issue is pending verification and/or reproduction
#4651
opened Oct 10, 2024 by
joonho3020
sta
command hangs on some designs
pending-verification
#4648
opened Oct 9, 2024 by
lukbau
Co-simulation fails for $fa cell
pending-verification
This issue is pending verification and/or reproduction
#4638
opened Oct 7, 2024 by
RCoeurjoly
tee -q -o <bad-path>
fails silently
pending-verification
#4636
opened Oct 7, 2024 by
povik
Previous Next
ProTip!
Type g i on any issue or pull request to go back to the issue listing page.