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synth_xilinx error in simple demo #4816

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lehaifeng000 opened this issue Dec 13, 2024 · 3 comments
Open

synth_xilinx error in simple demo #4816

lehaifeng000 opened this issue Dec 13, 2024 · 3 comments
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@lehaifeng000
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Version

0.47

On which OS did this happen?

Linux

Reproduction Steps

image

command: yosys -p "synth_xilinx -flatten -nowidelut -arch xc7 -top top; json -o synth.json top;" top.v

top.v

module top(
    input wire clk,  
    input key1,
    output led  
);
    FDRE fdre_inst2(
        .C(clk),
        .D(~key1),
        .CE(1'b1),
        .Q(led)
    );

endmodule

Expected Behavior

no

Actual Behavior

no

@lehaifeng000 lehaifeng000 added the pending-verification This issue is pending verification and/or reproduction label Dec 13, 2024
@lehaifeng000
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error message:

2.47. Executing XILINX_DFFOPT pass (optimize FF control signal usage).
Optimizing FFs in top.
terminate called after throwing an instance of 'std::out_of_range'
what(): dict::at()
[1] 31402 IOT instruction (core dumped) /home/lhf/src/eda/yosys/yosys -p top.v

@nakengelhardt nakengelhardt added bug and removed pending-verification This issue is pending verification and/or reproduction labels Dec 13, 2024
@nakengelhardt
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The code in xilinx_dffopt didn't consider the case of unconnected ports. Until this is fixed, you can avoid running into this bug by assigning something to the R port of FDRE:

module top(
    input wire clk,  
    input key1,
    output led  
);
    FDRE fdre_inst2(
        .C(clk),
        .D(~key1),
        .CE(1'b1),
        .Q(led),
        .R(1'b0)
    );

endmodule

@lehaifeng000
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The code in xilinx_dffopt didn't consider the case of unconnected ports. Until this is fixed, you can avoid running into this bug by assigning something to the R port of FDRE:

module top(
    input wire clk,  
    input key1,
    output led  
);
    FDRE fdre_inst2(
        .C(clk),
        .D(~key1),
        .CE(1'b1),
        .Q(led),
        .R(1'b0)
    );

endmodule

Thanks!

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