read delay of PICORV32_REGS must be 0?

[filamoon]

In picosoc.v, I noticed that the read data outputs (rdata1, rdata2) of "module picosoc_regs" are combination out, directly implemented using wire "assign".

Does this mean the read delay of picosoc_regs must be 0? This seems a very tough requirement.

[filamoon]

FYI, I use a read-delay-1 implementation of picosoc_regs in the provided testbench.v, and the tests fail immediately.