wbm_sel_o == 0 during read transactions

[epsilon537]

The picorv32_wb state machine always sets wbm_sel_o to 0 during Wishbone read transactions:

				if (mem_valid) begin
					wbm_adr_o <= mem_addr;
					wbm_dat_o <= mem_wdata;
					wbm_we_o <= we;
					wbm_sel_o <= mem_wstrb;

During read transactions mem_wstrb will be 0, so wbm_sel_o gets set to 0. According to the Wishbone spec, sel_o also applies to read transactions, however. Shouldn't wbm_sel_o be set to 4'b1111 during read transactions?

[marketideas]

I just ran into this as well. I can't believe no one else has found this. Trying to implement the OpenCores 16550 uart, and it requires wb_sel_o to be set during reads so it can properly return an 8 bit register (8 bit aligned) into a 32 bit data width.