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38 changes: 38 additions & 0 deletions
38
...inux/generic/backport-6.12/412-v6.14-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| From ae461cde5c559675fc4c0ba351c7c31ace705f56 Mon Sep 17 00:00:00 2001 | ||
| From: Bohdan Chubuk <chbgdn@gmail.com> | ||
| Date: Sun, 10 Nov 2024 22:50:47 +0200 | ||
| Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA001G | ||
|
|
||
| Add support for FORESEE F35SQA001G SPI NAND. | ||
|
|
||
| Similar to F35SQA002G, but differs in capacity. | ||
| Datasheet: | ||
| - https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf | ||
|
|
||
| Tested on Xiaomi AX3000T flashed with OpenWRT. | ||
|
|
||
| Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com> | ||
| Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> | ||
| --- | ||
| drivers/mtd/nand/spi/foresee.c | 10 ++++++++++ | ||
| 1 file changed, 10 insertions(+) | ||
|
|
||
| --- a/drivers/mtd/nand/spi/foresee.c | ||
| +++ b/drivers/mtd/nand/spi/foresee.c | ||
| @@ -81,6 +81,16 @@ static const struct spinand_info foresee | ||
| SPINAND_HAS_QE_BIT, | ||
| SPINAND_ECCINFO(&f35sqa002g_ooblayout, | ||
| f35sqa002g_ecc_get_status)), | ||
| + SPINAND_INFO("F35SQA001G", | ||
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71), | ||
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), | ||
| + NAND_ECCREQ(1, 512), | ||
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, | ||
| + &write_cache_variants, | ||
| + &update_cache_variants), | ||
| + SPINAND_HAS_QE_BIT, | ||
| + SPINAND_ECCINFO(&f35sqa002g_ooblayout, | ||
| + f35sqa002g_ecc_get_status)), | ||
| }; | ||
|
|
||
| static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { |
106 changes: 106 additions & 0 deletions
106
...ric/backport-6.12/781-15-v6.13-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,106 @@ | ||
| From 081c9c0265c91b8333165aa6230c20bcbc6f7cbf Mon Sep 17 00:00:00 2001 | ||
| From: Daniel Golle <daniel@makrotopia.org> | ||
| Date: Thu, 10 Oct 2024 14:07:16 +0100 | ||
| Subject: [PATCH 3/5] net: phy: realtek: read duplex and gbit master from PHYSR | ||
| register | ||
|
|
||
| The PHYSR MMD register is present and defined equally for all RTL82xx | ||
| Ethernet PHYs. | ||
| Read duplex and Gbit master bits from rtlgen_decode_speed() and rename | ||
| it to rtlgen_decode_physr(). | ||
|
|
||
| Signed-off-by: Daniel Golle <daniel@makrotopia.org> | ||
| Link: https://patch.msgid.link/b9a76341da851a18c985bc4774fa295babec79bb.1728565530.git.daniel@makrotopia.org | ||
| Signed-off-by: Paolo Abeni <pabeni@redhat.com> | ||
| --- | ||
| drivers/net/phy/realtek.c | 41 +++++++++++++++++++++++++++++++-------- | ||
| 1 file changed, 33 insertions(+), 8 deletions(-) | ||
|
|
||
| --- a/drivers/net/phy/realtek.c | ||
| +++ b/drivers/net/phy/realtek.c | ||
| @@ -80,15 +80,18 @@ | ||
|
|
||
| #define RTL822X_VND2_GANLPAR 0xa414 | ||
|
|
||
| -#define RTL822X_VND2_PHYSR 0xa434 | ||
| - | ||
| #define RTL8366RB_POWER_SAVE 0x15 | ||
| #define RTL8366RB_POWER_SAVE_ON BIT(12) | ||
|
|
||
| #define RTL9000A_GINMR 0x14 | ||
| #define RTL9000A_GINMR_LINK_STATUS BIT(4) | ||
|
|
||
| -#define RTLGEN_SPEED_MASK 0x0630 | ||
| +#define RTL_VND2_PHYSR 0xa434 | ||
| +#define RTL_VND2_PHYSR_DUPLEX BIT(3) | ||
| +#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) | ||
| +#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) | ||
| +#define RTL_VND2_PHYSR_MASTER BIT(11) | ||
| +#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) | ||
|
|
||
| #define RTL_GENERIC_PHYID 0x001cc800 | ||
| #define RTL_8211FVD_PHYID 0x001cc878 | ||
| @@ -660,9 +663,18 @@ static int rtl8366rb_config_init(struct | ||
| } | ||
|
|
||
| /* get actual speed to cover the downshift case */ | ||
| -static void rtlgen_decode_speed(struct phy_device *phydev, int val) | ||
| +static void rtlgen_decode_physr(struct phy_device *phydev, int val) | ||
| { | ||
| - switch (val & RTLGEN_SPEED_MASK) { | ||
| + /* bit 3 | ||
| + * 0: Half Duplex | ||
| + * 1: Full Duplex | ||
| + */ | ||
| + if (val & RTL_VND2_PHYSR_DUPLEX) | ||
| + phydev->duplex = DUPLEX_FULL; | ||
| + else | ||
| + phydev->duplex = DUPLEX_HALF; | ||
| + | ||
| + switch (val & RTL_VND2_PHYSR_SPEED_MASK) { | ||
| case 0x0000: | ||
| phydev->speed = SPEED_10; | ||
| break; | ||
| @@ -684,6 +696,19 @@ static void rtlgen_decode_speed(struct p | ||
| default: | ||
| break; | ||
| } | ||
| + | ||
| + /* bit 11 | ||
| + * 0: Slave Mode | ||
| + * 1: Master Mode | ||
| + */ | ||
| + if (phydev->speed >= 1000) { | ||
| + if (val & RTL_VND2_PHYSR_MASTER) | ||
| + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; | ||
| + else | ||
| + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; | ||
| + } else { | ||
| + phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; | ||
| + } | ||
| } | ||
|
|
||
| static int rtlgen_read_status(struct phy_device *phydev) | ||
| @@ -701,7 +726,7 @@ static int rtlgen_read_status(struct phy | ||
| if (val < 0) | ||
| return val; | ||
|
|
||
| - rtlgen_decode_speed(phydev, val); | ||
| + rtlgen_decode_physr(phydev, val); | ||
|
|
||
| return 0; | ||
| } | ||
| @@ -1007,11 +1032,11 @@ static int rtl822x_c45_read_status(struc | ||
| return 0; | ||
|
|
||
| /* Read actual speed from vendor register. */ | ||
| - val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR); | ||
| + val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); | ||
| if (val < 0) | ||
| return val; | ||
|
|
||
| - rtlgen_decode_speed(phydev, val); | ||
| + rtlgen_decode_physr(phydev, val); | ||
|
|
||
| return 0; | ||
| } |
54 changes: 54 additions & 0 deletions
54
...ric/backport-6.12/781-16-v6.13-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,54 @@ | ||
| From 68d5cd09e8919679ce13b85950debea4b2e98e04 Mon Sep 17 00:00:00 2001 | ||
| From: Daniel Golle <daniel@makrotopia.org> | ||
| Date: Thu, 10 Oct 2024 14:07:26 +0100 | ||
| Subject: [PATCH 4/5] net: phy: realtek: change order of calls in C22 | ||
| read_status() | ||
|
|
||
| Always call rtlgen_read_status() first, so genphy_read_status() which | ||
| is called by it clears bits in case auto-negotiation has not completed. | ||
| Also clear 10GBT link-partner advertisement bits in case auto-negotiation | ||
| is disabled or has not completed. | ||
|
|
||
| Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | ||
| Signed-off-by: Daniel Golle <daniel@makrotopia.org> | ||
| Link: https://patch.msgid.link/b15929a41621d215c6b2b57393368086589569ec.1728565530.git.daniel@makrotopia.org | ||
| Signed-off-by: Paolo Abeni <pabeni@redhat.com> | ||
| --- | ||
| drivers/net/phy/realtek.c | 22 +++++++++++++++------- | ||
| 1 file changed, 15 insertions(+), 7 deletions(-) | ||
|
|
||
| --- a/drivers/net/phy/realtek.c | ||
| +++ b/drivers/net/phy/realtek.c | ||
| @@ -949,17 +949,25 @@ static void rtl822xb_update_interface(st | ||
|
|
||
| static int rtl822x_read_status(struct phy_device *phydev) | ||
| { | ||
| - if (phydev->autoneg == AUTONEG_ENABLE) { | ||
| - int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); | ||
| + int lpadv, ret; | ||
|
|
||
| - if (lpadv < 0) | ||
| - return lpadv; | ||
| + ret = rtlgen_read_status(phydev); | ||
| + if (ret < 0) | ||
| + return ret; | ||
|
|
||
| - mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, | ||
| - lpadv); | ||
| + if (phydev->autoneg == AUTONEG_DISABLE || | ||
| + !phydev->autoneg_complete) { | ||
| + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); | ||
| + return 0; | ||
| } | ||
|
|
||
| - return rtlgen_read_status(phydev); | ||
| + lpadv = phy_read_paged(phydev, 0xa5d, 0x13); | ||
| + if (lpadv < 0) | ||
| + return lpadv; | ||
| + | ||
| + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); | ||
| + | ||
| + return 0; | ||
| } | ||
|
|
||
| static int rtl822xb_read_status(struct phy_device *phydev) |
30 changes: 30 additions & 0 deletions
30
...ric/backport-6.12/781-17-v6.13-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,30 @@ | ||
| From 5cb409b3960e75467cbb0a8e1e5596b4490570e3 Mon Sep 17 00:00:00 2001 | ||
| From: Daniel Golle <daniel@makrotopia.org> | ||
| Date: Thu, 10 Oct 2024 14:07:39 +0100 | ||
| Subject: [PATCH 5/5] net: phy: realtek: clear 1000Base-T link partner | ||
| advertisement | ||
|
|
||
| Clear 1000Base-T link partner advertisement bits in Clause-45 | ||
| read_status() function in case auto-negotiation is disabled or has not | ||
| been completed. | ||
|
|
||
| Signed-off-by: Daniel Golle <daniel@makrotopia.org> | ||
| Link: https://patch.msgid.link/9dc9b47b2d675708afef3ad366bfd78eb584d958.1728565530.git.daniel@makrotopia.org | ||
| Signed-off-by: Paolo Abeni <pabeni@redhat.com> | ||
| --- | ||
| drivers/net/phy/realtek.c | 4 ++++ | ||
| 1 file changed, 4 insertions(+) | ||
|
|
||
| --- a/drivers/net/phy/realtek.c | ||
| +++ b/drivers/net/phy/realtek.c | ||
| @@ -1026,6 +1026,10 @@ static int rtl822x_c45_read_status(struc | ||
| if (ret < 0) | ||
| return ret; | ||
|
|
||
| + if (phydev->autoneg == AUTONEG_DISABLE || | ||
| + !genphy_c45_aneg_done(phydev)) | ||
| + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 0); | ||
| + | ||
| /* Vendor register as C45 has no standardized support for 1000BaseT */ | ||
| if (phydev->autoneg == AUTONEG_ENABLE) { | ||
| val = phy_read_mmd(phydev, MDIO_MMD_VEND2, |
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