Verilog-to-PyG - Verilog-to-PyG – A framework for Graph Learning on RTL Designs

V2PYG is a EDA toolflow interface to support graph learning data preparation and functional equivalent data augmentation.

Brief

Our framework is implemented in ABC (https://github.com/berkeley-abc/abc) including graph extraction and logic optimization based combinational augmentation, which returns the structural edgelist and initial functional embedding for graph learning. The labels can be extracted from any stage in the downstream OpenROAD (https://github.com/The-OpenROAD-Project/OpenROAD) design flow.

Tutorials

Please visit https://yu-maryland.github.io/Verilog-to-PyG/

Reference

Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu. "Verilog-to-PyG – A Framework for Graph Learning and Augmentation on RTL Designs." ICCAD'23.

Tutorials

• Installations
• Pre-Tutorials
• Tutorial - Example 1 - Boolean Networks
• Tutorial - Example 2 - Mapped netlist
• Tutorial - Example 3 - Sequential
• Tutorial - Example 4 - RTL augmentaion