Skip to content

Release: v6.0 #5

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: dsPIC33A-M6
Choose a base branch
from
Open

Release: v6.0 #5

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c227f3a
cmake: Modify cmake for deleting logic of symlink
MuhammedZamroodh Nov 5, 2025
26d472b
Release: v6.0
MuhammedZamroodh Oct 15, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion arch/dspic/core/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ zephyr_library_sources(
isr_wrapper.S
prep_c.c
thread.c
swap.c
swap.S
tls.c
reset0.S
init.S
Expand Down
283 changes: 32 additions & 251 deletions arch/dspic/core/isr_wrapper.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,15 +4,9 @@
*/
#include <zephyr/devicetree.h>
#include <offsets.h>
#include <kernel_arch_swap_macro.S>
#define OFFSET DT_PROP(DT_NODELABEL(intc0), if_offset)

#if defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK512MPS512)
#define RAM_END 0x00013FFC
#elif defined(CONFIG_BOARD_DSPIC33A_CURIOSITY_P33AK128MC106)
#define RAM_END 0x00007FFC
#endif


.equ IF_OFFSET, OFFSET

.section .text,code
Expand All @@ -23,301 +17,88 @@
__COMMONInterrupt:
.section .isr.text._COMMONInterrupt,keep,code,keep
lnk #0x4
/* Handle ISR calls and clear handles IRQ
*/
mov.l w8, [w15++]
mov.sl #__kernel,w8
mov.sl #__kernel + ___cpu_t_nested_OFFSET,w8
add.l [w8],#1,[w8]
mov.w _INTTREGbits,w0
and.l #(0x1ff&0xFFFF),w0
and.l #0x1ff,w0
sub.l w0,#9,w0
mov.sl #__sw_isr_table,w1
sl.l w0,#3,w0
add.l w0,w1,w2
mov.l [w2+4],w1
mov.l [w2],w0


call w1
mov.w _INTTREGbits,w0
and.l #(0x1ff&0xFFFF),w0
and.l #0x1ff,w0
sub.l w0,#9,w0
call _arch_dspic_irq_clear


/* Check and perform context switch
*/
sub.l [w8],#1,w0
mov.l w0,[w8]
mov.l [--w15], w8
cp.l w0,#0
bra nz,.L2
mov.sl #__kernel+20,w1
mov.sl #__kernel + ___kernel_t_ready_q_OFFSET,w1
mov.l [w1],w1
mov.sl #__kernel+8,w0
mov.sl #__kernel + ___cpu_t_current_OFFSET,w0
mov.l [w0],w0
cp.l w1,w0
bra z,.L2
cp0.b _z_sys_post_kernel
bra z,.L2
mov.l [--w15], w8
ulnk
CTXTSWP #0x0
mov.l w0, [w15++]
mov.l #RAM_END, w0
mov.l w0, SPLIM
mov.l sr, w0
and #0xe0, w0
bra nz, 1f
mov.l [--w15], w0
ulnk
mov.l w2, [w15++]
mov.l w1, [w15++]
mov.l w0, [w15++]
mov.l #_swap_working_set, w0
mov.l [--w15], [w0++]
mov.l [--w15], [w0++]
mov.l [--w15], [w0]
mov.l [--w15], w1
mov.l sr, [w15++]
mov.l w1, [w15++]
mov.l [w0--], w2
mov.l [w0--], w1
mov.l [w0], w0
mov.l w0, [w15++]
1:
mov.l [--w15], w0
push RCOUNT
push.l fsr
push.l fcr
mov.l w0, [w15++]
mov.l w1, [w15++]
mov.l w2, [w15++]
mov.l w3, [w15++]
mov.l w4, [w15++]
mov.l w5, [w15++]
mov.l w6, [w15++]
mov.l w7, [w15++]
push.l f0
push.l f1
push.l f2
push.l f3
push.l f4
push.l f5
push.l f6
push.l f7
lnk #0x4

mov.l #__kernel, w0
mov.l #___cpu_t_current_OFFSET, w1
add w0, w1, w1
mov.l [w1], w2
mov.l #___thread_t_callee_saved_OFFSET, w1
add w2, w1, w1
z_dspic_save_caller_saved
z_dspic_save_callee_saved

mov.l w8, [w1++]
mov.l w9, [w1++]
mov.l w10, [w1++]
mov.l w11, [w1++]
mov.l w12, [w1++]
mov.l w13, [w1++]
mov.l w14, [w1++]
mov.l f8, [w1++]
mov.l f9, [w1++]
mov.l f10, [w1++]
mov.l f11, [w1++]
mov.l f12, [w1++]
mov.l f13, [w1++]
mov.l f14, [w1++]
mov.l f15, [w1++]
mov.l f16, [w1++]
mov.l f17, [w1++]
mov.l f18, [w1++]
mov.l f19, [w1++]
mov.l f20, [w1++]
mov.l f21, [w1++]
mov.l f22, [w1++]
mov.l f23, [w1++]
mov.l f24, [w1++]
mov.l f25, [w1++]
mov.l f26, [w1++]
mov.l f27, [w1++]
mov.l f28, [w1++]
mov.l f29, [w1++]
mov.l f30, [w1++]
mov.l f31, [w1++]
mov.l #RCOUNT, w2
mov.l [w2], [w1++]
mov.l #CORCON, w2
mov.l [w2], [w1++]
mov.l #MODCON, w2
mov.l [w2], [w1++]
mov.l #XMODSRT, w2
mov.l [w2], [w1++]
mov.l #XMODEND, w2
mov.l [w2], [w1++]
mov.l #YMODSRT, w2
mov.l [w2], [w1++]
mov.l #YMODEND, w2
mov.l [w2], [w1++]
mov.l #XBREV, w2
mov.l [w2], [w1++]
slac.l A, [W1++]
sac.l A, [W1++]
suac.l A, [W1++]
slac.l B, [W1++]
sac.l B, [W1++]
suac.l B, [W1++]
mov.l w15, [w1++]
mov.l w14, [w1++]
mov.l #SPLIM, w2
mov.l [w2], [w1++]
mov.l #__kernel_ready_q_cache_OFFSET, w2
mov.l [w2], w2
mov.l #__kernel_current_OFFSET, w1
mov.l w2, [w1]

mov.sl #__kernel+20,w0
mov.l [w0],w0
mov.sl #__kernel,w1
mov.l w0,[w1 + ___cpu_t_current_OFFSET]
mov.l [w0 + ___thread_t_tls_OFFSET],w0
rcall __set_tls

mov.l #__kernel, w0
mov.l #___cpu_t_current_OFFSET, w1
add w0, w1, w1
mov.l [w1], w2
mov.l #___thread_t_callee_saved_OFFSET, w1
add w2, w1, w1
#ifdef CONFIG_CURRENT_THREAD_USE_TLS
mov.l [w2 + ___thread_t_tls_OFFSET], w0
rcall __set_tls
#endif

mov.l [w1++], w8
mov.l [w1++], w9
mov.l [w1++], w10
mov.l [w1++], w11
mov.l [w1++], w12
mov.l [w1++], w13
mov.l [w1++], w14
mov.l [w1++], f8
mov.l [w1++], f9
mov.l [w1++], f10
mov.l [w1++], f11
mov.l [w1++], f12
mov.l [w1++], f13
mov.l [w1++], f14
mov.l [w1++], f15
mov.l [w1++], f16
mov.l [w1++], f17
mov.l [w1++], f18
mov.l [w1++], f19
mov.l [w1++], f20
mov.l [w1++], f21
mov.l [w1++], f22
mov.l [w1++], f23
mov.l [w1++], f24
mov.l [w1++], f25
mov.l [w1++], f26
mov.l [w1++], f27
mov.l [w1++], f28
mov.l [w1++], f29
mov.l [w1++], f30
mov.l [w1++], f31
mov.l #RCOUNT, w2
mov.l [w1++], [w2]
mov.l #CORCON, w2
mov.l [w1++], [w2]
mov.l #MODCON, w2
mov.l [w1++], [w2]
mov.l #XMODSRT, w2
mov.l [w1++], [w2]
mov.l #XMODEND, w2
mov.l [w1++], [w2]
mov.l #YMODSRT, w2
mov.l [w1++], [w2]
mov.l #YMODEND, w2
mov.l [w1++], [w2]
mov.l #XBREV, w2
mov.l [w1++], [w2]
clr A
clr B
llac.l [w1++], A
lac.l [w1++], A
luac.l [w1++], A
llac.l [w1++], B
lac.l [w1++], B
luac.l [w1++], B
mov.l [w1++], w15
mov.l [w1++], w14
mov.l #SPLIM, w2
mov.l [w1++], [w2]
z_dspic_restore_callee_saved
z_dspic_restore_caller_saved

ulnk
pop.l f7
pop.l f6
pop.l f5
pop.l f4
pop.l f3
pop.l f2
pop.l f1
pop.l f0
mov.l [--w15], w7
mov.l [--w15], w6
mov.l [--w15], w5
mov.l [--w15], w4
mov.l [--w15], w3
mov.l [--w15], w2
mov.l [--w15], w1
mov.l [--w15], w0
pop.l fcr
pop.l fsr
pop RCOUNT
mov.l w0, [w15++]
mov.l sr, w0
and #0xe0, w0
mov.l [--w15], w0
bra nz, 1f
mov.l w2, [w15++]
mov.l w1, [w15++]
mov.l w0, [w15++]
mov.l #_swap_working_set, w0
mov.l [--w15], [w0++]
mov.l [--w15], [w0++]
mov.l [--w15], [w0]
mov.l [--w15], w1
mov.l [--w15], w2
mov.l w2, sr
mov.l w1, [w15++]
mov.l [w0--], w2
mov.l [w0--], w1
mov.l [w0], w0
lnk #0x4
1:
mov.l w2, [w15++]
mov.l w1, [w15++]
mov.l w0, [w15++]
mov.sl #__kernel, w0
mov.l [w0 + ___cpu_t_current_OFFSET], w1
mov.l #___thread_t_arch_OFFSET, w2
add.l w2, w1, w1
mov.l [w1 + ___thread_arch_t_swapped_from_thread_OFFSET], w0
mov.sl #__kernel_current_OFFSET, w0
mov.l [w0], w1
mov.l [w1 + __thread_t_arch_swapped_from_thread_OFFSET], w0
mov.l #0, w2
cp.l w2, w0
mov.l [--w15], w0
bra z, 1f
mov.l [w1 + ___thread_arch_t_swap_return_value_OFFSET], w0
mov.l w2, [w1 + ___thread_arch_t_swapped_from_thread_OFFSET]
1:
bra z, 2f
mov.l [w1 + __thread_t_arch_swap_return_value_OFFSET], w0
mov.l w2, [w1 + __thread_t_arch_swapped_from_thread_OFFSET]
2:
mov.l [--w15], w1
mov.l [--w15], w2
nop
retfie



.L2:
mov.l [--w15], w8
ulnk
.L1:
retfie


.section .text._arch_dspic_irq_clear,code
.align 4
.global _arch_dspic_irq_clear ; export
.type _arch_dspic_irq_clear,@function
_arch_dspic_irq_clear:

GTEXT(arch_dspic_irq_clear)
SECTION_FUNC(TEXT, arch_dspic_irq_clear)
lnk #0
lsr.l w0,#5,w1
sl.l w1,#2,w1
Expand Down
1 change: 1 addition & 0 deletions arch/dspic/core/offsets/offsets.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
#include <zephyr/kernel.h>
#include <kernel_offsets.h>

GEN_OFFSET_SYM(_thread_arch_t, cpu_level);
GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
GEN_OFFSET_SYM(_thread_arch_t, swapped_from_thread);

Expand Down
Loading
Loading