How register is accessed for different operand sizes?

[DarkC343]

In PTX, operands have type and size information. I assume that each register size in baseline architecture is of 4 bytes. My questions are about the register access flow:

• For wider registers, like 64-bit or 128-bit, do we access multiple 4-byte registers? Or do we access 8- or 16-byte registers in single access?
• How about operands narrower than 4-byte (eg. 8-bit, 16-bit)?

[JRPan]

In terms of occupancy, yes, that is considered.
In the timing model, I don't think so.