Add support for nrf52833 (including bluetooth) and softdevice S113 7.2.0

cores/nRF5/HardwarePWM.h

@@ -40,7 +40,7 @@
 #include "nrf.h"
 #include <atomic>
 
-#ifdef NRF52840_XXAA
+#if defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
 #define HWPWM_MODULE_NUM    4
 #else
 #define HWPWM_MODULE_NUM    3

cores/nRF5/HardwareSerial.h

@@ -49,7 +49,7 @@
 #ifdef NRF52832_XXAA
   #define SERIAL_8N1	(UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos)
   #define SERIAL_8E1	(UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos)
-#elif defined(NRF52840_XXAA)
+#elif defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
   #define SERIAL_8N1	((UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos))
   #define SERIAL_8N2	((UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos))
   #define SERIAL_8E1	((UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos))

cores/nRF5/WString.cpp

@@ -123,7 +123,7 @@ String::String(double value, unsigned char decimalPlaces)
 
 String::~String()
 {
-	free(buffer);
+	invalidate();
 }
 
 /*********************************************/

cores/nRF5/linker/gcc_startup_nrf52840.S

@@ -20,7 +20,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
 
 */
 
-#ifdef NRF52840_XXAA
+#if defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
 
     .syntax unified
     .arch armv7e-m

cores/nRF5/linker/nrf52833_s113_v7.ld

@@ -0,0 +1,38 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x1C000, LENGTH = 0x7D000 - 0x1C000
+
+  /* SRAM required by S113 depend on
+   * - Attribute Table Size (Number of Services and Characteristics)
+   * - Vendor UUID count
+   * - Max ATT MTU
+   * - Concurrent connection peripheral + central + secure links
+   * - Event Len, HVN queue, Write CMD queue
+   */ 
+  RAM (rwx) :  ORIGIN = 0x20006000, LENGTH = 0x20020000 - 0x20006000
+}
+
+SECTIONS
+{
+  . = ALIGN(4);
+  .svc_data :
+  {
+    PROVIDE(__start_svc_data = .);
+    KEEP(*(.svc_data))
+    PROVIDE(__stop_svc_data = .);
+  } > RAM
+
+  .fs_data :
+  {
+    PROVIDE(__start_fs_data = .);
+    KEEP(*(.fs_data))
+    PROVIDE(__stop_fs_data = .);
+  } > RAM
+} INSERT AFTER .data;
+
+INCLUDE "nrf52_common.ld"

cores/nRF5/linker/nrf52833_s140_v6.ld

@@ -0,0 +1,41 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  /* 0x6d000 end address comes from bootloader flash starting at 0x74000
+  and LFS_FLASH_ADDR with LFS_FLASH_TOTAL_SIZE * 4096 bytes sitting below that address.
+  */
+  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0x6D000 - 0x26000
+
+  /* SRAM required by S140 depend on
+   * - Attribute Table Size (Number of Services and Characteristics)
+   * - Vendor UUID count
+   * - Max ATT MTU
+   * - Concurrent connection peripheral + central + secure links
+   * - Event Len, HVN queue, Write CMD queue
+   */ 
+  RAM (rwx) :  ORIGIN = 0x20006000, LENGTH = 0x20020000 - 0x20006000
+}
+
+SECTIONS
+{
+  . = ALIGN(4);
+  .svc_data :
+  {
+    PROVIDE(__start_svc_data = .);
+    KEEP(*(.svc_data))
+    PROVIDE(__stop_svc_data = .);
+  } > RAM
+
+  .fs_data :
+  {
+    PROVIDE(__start_fs_data = .);
+    KEEP(*(.fs_data))
+    PROVIDE(__stop_fs_data = .);
+  } > RAM
+} INSERT AFTER .data;
+
+INCLUDE "nrf52_common.ld"

cores/nRF5/linker/nrf52840_s113_v7.ld

@@ -0,0 +1,38 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x1C000, LENGTH = 0xED000 - 0x1C000
+
+  /* SRAM required by S113 depend on
+   * - Attribute Table Size (Number of Services and Characteristics)
+   * - Vendor UUID count
+   * - Max ATT MTU
+   * - Concurrent connection peripheral + central + secure links
+   * - Event Len, HVN queue, Write CMD queue
+   */ 
+  RAM (rwx) :  ORIGIN = 0x20006000, LENGTH = 0x20040000 - 0x20006000
+}
+
+SECTIONS
+{
+  . = ALIGN(4);
+  .svc_data :
+  {
+    PROVIDE(__start_svc_data = .);
+    KEEP(*(.svc_data))
+    PROVIDE(__stop_svc_data = .);
+  } > RAM
+
+  .fs_data :
+  {
+    PROVIDE(__start_fs_data = .);
+    KEEP(*(.fs_data))
+    PROVIDE(__stop_fs_data = .);
+  } > RAM
+} INSERT AFTER .data;
+
+INCLUDE "nrf52_common.ld"

cores/nRF5/new.cpp

@@ -23,27 +23,27 @@
 #include <sys/stat.h>
 #include <malloc.h>
 
-void *operator new(size_t size) {
+void __attribute__((weak)) *operator new(size_t size) {
   return rtos_malloc(size);
 }
 
-void *operator new[](size_t size) {
+void __attribute__((weak)) *operator new[](size_t size) {
   return rtos_malloc(size);
 }
 
-void operator delete(void * ptr) {
+void __attribute__((weak)) operator delete(void * ptr) {
   rtos_free(ptr);
 }
 
-void operator delete[](void * ptr) {
+void __attribute__((weak)) operator delete[](void * ptr) {
   rtos_free(ptr);
 }
 
-void operator delete(void * ptr, unsigned int) {
+void __attribute__((weak)) operator delete(void * ptr, unsigned int) {
   rtos_free(ptr);
 }
 
-void operator delete[](void * ptr, unsigned int) {
+void __attribute__((weak)) operator delete[](void * ptr, unsigned int) {
   rtos_free(ptr);
 }
 

cores/nRF5/nordic/nrfx/drivers/include/nrfx_clock.h

@@ -106,15 +106,16 @@ void nrfx_clock_stop(nrf_clock_domain_t domain);
  *
  * XTAL source is assumed for domains with multiple sources.
  *
- * @param[in]  domain  Clock domain.
- * @param[out] clk_src Clock source that is running. Set to NULL if not needed.
- *                     Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for
- *                     LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M.
+ * @param[in]  domain    Clock domain.
+ * @param[out] p_clk_src Pointer to a clock source that is running. Set to NULL if not needed.
+ *                       Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src
+ *                       must be of either @ref nrf_clock_lfclk_t type for LFCLK
+ *                       or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M.
  *
  * @retval true  The clock domain is running.
  * @retval false The clock domain is not running.
  */
-NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src);
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src);
 
 #if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M
 /**
@@ -318,9 +319,9 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event)
     return nrf_clock_event_address_get(NRF_CLOCK, event);
 }
 
-NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src)
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src)
 {
-    return nrf_clock_is_running(NRF_CLOCK, domain, clk_src);
+    return nrf_clock_is_running(NRF_CLOCK, domain, p_clk_src);
 }
 
 NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void)

cores/nRF5/nordic/nrfx/drivers/include/nrfx_nfct.h

@@ -164,6 +164,9 @@ typedef struct
  * @brief Callback descriptor to pass events from the NFCT driver to the upper layer.
  *
  * @param[in] p_event Pointer to the event descriptor.
+ *
+ * @note @ref NRFX_NFCT_EVT_FIELD_DETECTED and @ref NRFX_NFCT_EVT_FIELD_LOST are generated only on field state transitions,
+ *       i.e. there will be no multiple events of the same type (out of the 2 mentioned) coming in a row.
  */
 typedef void (*nrfx_nfct_handler_t)(nrfx_nfct_evt_t const * p_event);
 
@@ -265,6 +268,9 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
 /**
  * @brief Function for getting default bytes for NFCID1.
  *
+ * @note This function cannot be used from the non-secure code because it requires access
+ *       to FICR registers.
+ *
  * @param[in,out] p_nfcid1_buff    In:  empty buffer for data;
  *                                 Out: buffer with the NFCID1 default data. These values
  *                                      can be used to fill the Type 2 Tag Internal Bytes.

cores/nRF5/nordic/nrfx/drivers/include/nrfx_nvmc.h

@@ -154,6 +154,37 @@ bool nrfx_nvmc_byte_writable_check(uint32_t address, uint8_t value);
  */
 void nrfx_nvmc_byte_write(uint32_t address, uint8_t value);
 
+/**
+ * @brief Function for checking whether a halfword is writable at the specified address.
+ *
+ * The NVMC is only able to write '0' to bits in the Flash that are erased (set to '1').
+ * It cannot rewrite a bit back to '1'. This function checks if the value currently
+ * residing at the specified address can be transformed to the desired value
+ * without any '0' to '1' transitions.
+ *
+ * @param address Address to be checked. Must be halfword-aligned.
+ * @param value   Value to be checked.
+ *
+ * @retval true  Halfword can be written at the specified address.
+ * @retval false Halfword cannot be written at the specified address.
+ *               Erase page or change address.
+ */
+bool nrfx_nvmc_halfword_writable_check(uint32_t address, uint16_t value);
+
+/**
+ * @brief Function for writing a 16-bit halfword to flash.
+ *
+ * To determine if the flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ *       the CPU may be halted during the operation.
+ *       Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to. Must be halfword-aligned.
+ * @param value   Value to write.
+ */
+void nrfx_nvmc_halfword_write(uint32_t address, uint16_t value);
+
 /**
  * @brief Function for checking whether a word is writable at the specified address.
  *
@@ -215,6 +246,19 @@ void nrfx_nvmc_bytes_write(uint32_t address, void const * src, uint32_t num_byte
  */
 void nrfx_nvmc_words_write(uint32_t address, void const * src, uint32_t num_words);
 
+/**
+ * @brief Function for reading a 16-bit aligned halfword from the OTP (UICR)
+ *
+ * OTP is a region of the UICR present in some chips. This function must be used
+ * to read halfword data from this region since unaligned accesses are not
+ * available on the OTP flash area.
+ *
+ * @param address Address to read from. Must be halfword-aligned.
+ *
+ * @retval The contents at @p address.
+ */
+uint16_t nrfx_nvmc_otp_halfword_read(uint32_t address);
+
 /**
  * @brief Function for getting the total flash size in bytes.
  *

cores/nRF5/nordic/nrfx/drivers/include/nrfx_spim.h

@@ -285,6 +285,7 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance);
  * - @ref NRFX_SPIM_FLAG_HOLD_XFER - Driver is not starting the transfer. Use this
  *   flag if the transfer is triggered externally by PPI. Use
  *   @ref nrfx_spim_start_task_get to get the address of the start task.
+ *   Chip select must be configured to @ref NRFX_SPIM_PIN_NOT_USED and managed outside the driver.
  * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER - No user event handler after transfer
  *   completion. This also means no interrupt at the end of the transfer.
  *   If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into

cores/nRF5/nordic/nrfx/drivers/include/nrfx_uarte.h

@@ -296,6 +296,15 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
  *       to be placed in the Data RAM region. If this condition is not met,
  *       this function fails with the error code NRFX_ERROR_INVALID_ADDR.
  *
+ * @warning When the double-buffering feature is used and the UARTE interrupt
+ *          is processed with a delay (for example, due to a higher priority interrupt)
+ *          long enough for both buffers to get filled completely,
+ *          the event handler will be invoked only once, to notify that
+ *          the first buffer has been filled. This is because from hardware perspective it
+ *          is impossible to deduce in such case if the second buffer was also filled completely or not.
+ *          To prevent this from happening, keep the UARTE interrupt latency low
+ *          or use large enough reception buffers.
+ *
  * @param[in] p_instance Pointer to the driver instance structure.
  * @param[in] p_data     Pointer to data.
  * @param[in] length     Number of bytes to receive. Maximum possible length is
@@ -334,6 +343,16 @@ bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance);
  *       It will contain number of bytes received until the abort was called. The event
  *       handler will be called from the UARTE interrupt context.
  *
+ * @warning When the double-buffering feature is used and the UARTE interrupt
+ *          is processed with a delay (for example, due to a higher priority
+ *          interrupt) long enough for the first buffer to be filled completely,
+ *          the event handler will be supplied with the pointer to the first
+ *          buffer and the number of bytes received in the second buffer.
+ *          This is because from hardware perspective it is impossible to deduce
+ *          the reception of which buffer has been aborted.
+ *          To prevent this from happening, keep the UARTE interrupt latency low
+ *          or use large enough reception buffers.
+ *
  * @param[in] p_instance Pointer to the driver instance structure.
  */
 void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance);