Add option to define order of pin matrix assignments

.gitignore

@@ -21,6 +21,7 @@ fp-info-cache
 
 # Netlist files (exported from Eeschema)
 *.net
+!tests/test_netlist_generation/*.net
 
 # Autorouter files (exported from Pcbnew)
 *.dsn

src/kle2netlist/__main__.py

@@ -45,14 +45,21 @@ def main(
     diode_footprint: str = typer.Option(
         "Diode_SMD:D_SOD-123F", "-df", "--diode-footprint", help="Diode footprint"
     ),
-    lib_paths: Optional[List[str]] = typer.Option(
+    # use this feature https://github.com/fastapi/typer/pull/800 when merged:
+    lib_paths: Optional[str] = typer.Option(
         None, "-l", "--lib-path", help="Path to symbol library"
     ),
     controller_circuit: ControllerCircuit = typer.Option(
         ControllerCircuit.NONE,
         "--controller-circuit",
         help="Add microcontroller circuitry",
     ),
+    # use this feature https://github.com/fastapi/typer/pull/800 when merged:
+    row_column_pin_order: Optional[str] = typer.Option(
+        None,
+        "--row-column-pin-order",
+        help="Comma separated list of microcontroller pins defining order of row/column assignments",
+    ),
     version: bool = typer.Option(
         None,
         "-v",
@@ -83,7 +90,10 @@ def main(
             stabilizer_footprint=stabilizer_footprint,
             diode_footprint=diode_footprint,
             controller_circuit=controller_circuit,
-            additional_search_path=lib_paths,
+            additional_search_path=lib_paths.split(",") if lib_paths else None,
+            row_column_pin_order=(
+                row_column_pin_order.split(",") if row_column_pin_order else None
+            ),
         )
 
         generate_netlist(circuit, output)

src/kle2netlist/circuits/__init__.py

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: MIT
 from dataclasses import dataclass, fields
 from enum import Enum
-from typing import Dict, List
+from typing import Dict, List, Optional
 
 from kbplacer.element_position import Side
 from skidl import Net
@@ -76,9 +76,16 @@ class ControllerCircuit(str, Enum):
     NONE = "none"
     ATMEGA32U4_AU_V1 = "atmega32u4_au_v1"
 
-    def add(self, rows: Dict[str, Net], columns: Dict[str, Net]) -> None:
+    def add(
+        self,
+        rows: Dict[str, Net],
+        columns: Dict[str, Net],
+        row_column_pin_order: Optional[List[str]] = None,
+    ) -> None:
         if self == ControllerCircuit.ATMEGA32U4_AU_V1:
-            atmega32u4.circuit(rows, columns, "v1")
+            atmega32u4.circuit(
+                rows, columns, "v1", row_column_pin_order=row_column_pin_order
+            )
 
     def positions(self) -> List[Footprint]:
         if self == ControllerCircuit.ATMEGA32U4_AU_V1:

src/kle2netlist/circuits/atmega32u4.py

@@ -1,7 +1,7 @@
 # SPDX-FileCopyrightText: 2024-present adamws <adamws@users.noreply.github.com>
 #
 # SPDX-License-Identifier: MIT
-from typing import Dict
+from typing import Dict, List, Optional
 
 import skidl
 
@@ -247,8 +247,13 @@
 
 
 @skidl.subcircuit
-def atmega32u4(rows: Dict[str, skidl.Net], columns: Dict[str, skidl.Net], footprints):
-    assignment_order = ATMEGA32U4AU_PIN_ASSIGN_ORDER[:]
+def atmega32u4(
+    rows: Dict[str, skidl.Net],
+    columns: Dict[str, skidl.Net],
+    footprints,
+    row_column_pin_order: List[str],
+):
+    assignment_order = row_column_pin_order[:]
     num_rows = len(rows)
     num_columns = len(columns)
     num_pins = len(assignment_order)
@@ -369,13 +374,22 @@ def atmega32u4(rows: Dict[str, skidl.Net], columns: Dict[str, skidl.Net], footpr
     gnd += button[1]
 
     for _, row in rows.items():
-        row += uc[assignment_order.pop(0)]
+        pin = assignment_order.pop(0)
+        row += uc[pin]
     for _, column in columns.items():
         column += uc[assignment_order.pop(0)]
 
 
-def circuit(rows: Dict[str, skidl.Net], columns: Dict[str, skidl.Net], variant: str):
-    atmega32u4(rows, columns, FOOTPRINTS[variant])
+def circuit(
+    rows: Dict[str, skidl.Net],
+    columns: Dict[str, skidl.Net],
+    variant: str,
+    *,
+    row_column_pin_order: Optional[List[str]] = None,
+):
+    if not row_column_pin_order:
+        row_column_pin_order = ATMEGA32U4AU_PIN_ASSIGN_ORDER
+    atmega32u4(rows, columns, FOOTPRINTS[variant], row_column_pin_order)
 
 
 if __name__ == "__main__":

src/kle2netlist/netlist.py

@@ -19,6 +19,7 @@ def build_circuit(
     stabilizer_footprint: str,
     diode_footprint: str,
     controller_circuit: ControllerCircuit = ControllerCircuit.NONE,
+    row_column_pin_order: Optional[List[str]] = None,
     additional_search_path: Optional[List[str]] = None,
 ) -> skidl.Circuit:
     set_skidl_search_path(additional_search_path)
@@ -29,7 +30,7 @@ def build_circuit(
         rows, columns = handle_switch_matrix(
             keyboard, switch_footprint, diode_footprint, stabilizer_footprint
         )
-        controller_circuit.add(rows, columns)
+        controller_circuit.add(rows, columns, row_column_pin_order=row_column_pin_order)
     return circuit
 
 

tests/test_netlist_generation.py

@@ -38,15 +38,34 @@ def assert_netlist(netlist_template, result_file, template_dict):
     result_netlist.close()
 
 
+@pytest.fixture
+def file_isolation(tmpdir, request):
+    def _copy_files(layout_filename, netlist_template) -> None:
+        filename = request.module.__file__
+        test_dir, _ = os.path.splitext(filename)
+
+        if os.path.isdir(test_dir):
+            shutil.copy(f"{test_dir}/{layout_filename}", tmpdir)
+            shutil.copy(f"{test_dir}/{netlist_template}", tmpdir)
+
+    return _copy_files
+
+
 @pytest.mark.parametrize(
-    ("layout_filename", "netlist_template", "controller_circuit"),
+    (
+        "layout_filename",
+        "netlist_template",
+        "controller_circuit",
+        "row_column_pin_order",
+    ),
     [
         # fmt: off
-        ("2x2.json", "2x2.net", ControllerCircuit.NONE),
-        ("2x2.json", "2x2-with-uc.net", ControllerCircuit.ATMEGA32U4_AU_V1),
-        ("2x2-with-alternative-layout.json", "2x2-with-alternative-layout.net", ControllerCircuit.NONE),
-        ("iso-enter.json", "iso-enter.net", ControllerCircuit.NONE),
-        ("empty.json", "empty-with-uc.net", ControllerCircuit.ATMEGA32U4_AU_V1),
+        ("2x2.json", "2x2.net", ControllerCircuit.NONE, None),
+        ("2x2.json", "2x2-with-uc.net", ControllerCircuit.ATMEGA32U4_AU_V1, None),
+        ("2x2.json", "2x2-with-uc-custom-order.net", ControllerCircuit.ATMEGA32U4_AU_V1, ["PD0", "PD1", "PF0", "PF1"]),
+        ("2x2-with-alternative-layout.json", "2x2-with-alternative-layout.net", ControllerCircuit.NONE, None),
+        ("iso-enter.json", "iso-enter.net", ControllerCircuit.NONE, None),
+        ("empty.json", "empty-with-uc.net", ControllerCircuit.ATMEGA32U4_AU_V1, None),
         # fmt: on
     ],
 )
@@ -58,23 +77,12 @@ class TestNetlistGeneration:
         "stabilizer_footprint_2u": "PCM_lib2:ST_2.00u",
     }
 
-    @pytest.fixture
-    def file_isolation(self, tmpdir, request):
-        def _copy_files(layout_filename, netlist_template) -> None:
-            filename = request.module.__file__
-            test_dir, _ = os.path.splitext(filename)
-
-            if os.path.isdir(test_dir):
-                shutil.copy(f"{test_dir}/{layout_filename}", tmpdir)
-                shutil.copy(f"{test_dir}/{netlist_template}", tmpdir)
-
-        return _copy_files
-
     def test_api(
         self,
         layout_filename,
         netlist_template,
         controller_circuit,
+        row_column_pin_order,
         file_isolation,
         tmpdir,
     ) -> None:
@@ -87,6 +95,7 @@ def test_api(
             stabilizer_footprint="PCM_lib2:ST_{:.2f}u",
             diode_footprint="Diode_SMD:D_SOD-323F",
             controller_circuit=controller_circuit,
+            row_column_pin_order=row_column_pin_order,
         )
         generate_netlist(circuit, result_netlist_path)
 
@@ -99,23 +108,27 @@ def test_cli(
         layout_filename,
         netlist_template,
         controller_circuit,
+        row_column_pin_order,
         file_isolation,
         tmpdir,
     ) -> None:
         file_isolation(layout_filename, netlist_template)
         result_netlist_path = tmpdir.join("test.net")
 
         # fmt: off
-        result = runner.invoke(app, [
+        args = [
             "--layout", tmpdir.join(layout_filename),
             "--output", result_netlist_path,
             "--switch-footprint", "PCM_lib1:SW_{:.2f}u",
             "--stabilizer-footprint", "PCM_lib2:ST_{:.2f}u",
             "--diode-footprint", "Diode_SMD:D_SOD-323F",
             "--controller-circuit", controller_circuit,
-            ],
-        )
+        ]
         # fmt: on
+        if row_column_pin_order:
+            args.append("--row-column-pin-order")
+            args.append(",".join(row_column_pin_order))
+        result = runner.invoke(app, args)
         assert result.exit_code == 0
 
         assert_netlist(