Fixed code to write firmware design and inverse tables for the TC. (c…

…ms-sw#33)
aehart · Sep 23, 2020 · ab3d8e2 · ab3d8e2
1 parent 4c616ef
commit ab3d8e2
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Showing 9 changed files with 455 additions and 749 deletions.
diff --git a/L1Trigger/TrackFindingTracklet/interface/ProcessBase.h b/L1Trigger/TrackFindingTracklet/interface/ProcessBase.h
@@ -32,7 +32,7 @@ namespace trklet {
     //This function processes the name of a TE module to determine the layerdisks and iseed
     void initLayerDisksandISeed(unsigned int& layerdisk1, unsigned int& layerdisk2, unsigned int& iSeed);
 
-    unsigned int getISeed(std::string name);
+    unsigned int getISeed(const std::string& name);
 
   protected:
     std::string name_;

diff --git a/L1Trigger/TrackFindingTracklet/interface/TrackletCalculator.h b/L1Trigger/TrackFindingTracklet/interface/TrackletCalculator.h
@@ -14,6 +14,8 @@ namespace trklet {
   class MemoryBase;
   class AllStubsMemory;
   class StubPairsMemory;
+  class VarInv;
+  class VarBase;
 
   class TrackletCalculator : public TrackletCalculatorBase {
   public:
@@ -33,6 +35,9 @@ namespace trklet {
     std::vector<AllStubsMemory*> innerallstubs_;
     std::vector<AllStubsMemory*> outerallstubs_;
     std::vector<StubPairsMemory*> stubpairs_;
+
+    void writeInvTable(void (*writeLUT)(const VarInv&, const std::string&));
+    void writeFirmwareDesign(void (*writeDesign)(const std::vector<VarBase*>&, const std::string&));
   };
 };  // namespace trklet
 #endif
diff --git a/L1Trigger/TrackFindingTracklet/interface/imath.h b/L1Trigger/TrackFindingTracklet/interface/imath.h
@@ -271,10 +271,10 @@ namespace trklet {
     void pipe_increment() { pipe_counter_++; }
     void add_delay(int i) { pipe_delays_.push_back(i); }
     bool has_delay(int i);  //returns true if already have this variable delayed.
-    static void verilog_print(std::vector<VarBase *> v, std::ofstream &fs) { design_print(v, fs, verilog); }
-    static void hls_print(std::vector<VarBase *> v, std::ofstream &fs) { design_print(v, fs, hls); }
-    static void design_print(std::vector<VarBase *> v, std::ofstream &fs, Verilog);
-    static void design_print(std::vector<VarBase *> v, std::ofstream &fs, HLS);
+    static void verilog_print(const std::vector<VarBase *>& v, std::ofstream &fs) { design_print(v, fs, verilog); }
+    static void hls_print(const std::vector<VarBase *>& v, std::ofstream &fs) { design_print(v, fs, hls); }
+    static void design_print(const std::vector<VarBase *>& v, std::ofstream &fs, Verilog);
+    static void design_print(const std::vector<VarBase *>& v, std::ofstream &fs, HLS);
     static std::string pipe_delay(VarBase *v, int nbits, int delay);
     std::string pipe_delays(const int step);
     static std::string pipe_delay_wire(VarBase *v, std::string name_delayed, int nbits, int delay);