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  1. Synthetic-Training-Data-Generator-for-Tesseract-Arabic Synthetic-Training-Data-Generator-for-Tesseract-Arabic Public

    This is a synthetic training data generator for Tesseract 4.0+ Arabic

    Python 4 1

  2. SAR-ADC-Controller SAR-ADC-Controller Public

    This is a SAR ADC Controller verilog implementation

    Verilog 2 3

  3. RCA-CLA-CSA-Signed-Unsigned-nxm-Multiplier RCA-CLA-CSA-Signed-Unsigned-nxm-Multiplier Public

    This is an implementation of some adders: Ripple Carry Adder, Carry Select Adder, and Carry Lookahead Adder. And nxm dynamic parallel multipliers: Signed, and Unsigned using Verilog

    Verilog 2 1

  4. Serial-Parallel-Multiplier-Verilog Serial-Parallel-Multiplier-Verilog Public

    This is a Serial Parallel Multiplier coded in Verilog

    Verilog 1 1

  5. Network-Congestion-Resolver-Matlab Network-Congestion-Resolver-Matlab Public

    This is a car network congestion resolver coded in matlab

    MATLAB 1

  6. VDCS-Prototype-2 VDCS-Prototype-2 Public

    This is an experiment for milestone 2 using Go. Includes an implementation of circuit garbling and evaluation based on Yao's Garbled Circuit Protocol.

    Go 1