Added imporved Card reset scheme

Updated python script to set nand bit on 0x1b8. SCFG_EXT no longer has
to be manually set to allow SD access.

Also proper access control settings now used and the improved card reset
code from NTR Launcher now integrated into NitroHax.

Now NitroHax will skip card reset if card was inserted on boot. If card
was not inserted or slot is powered down for another reason, then it
performs a slot power on. The code used to power off the slot is
currently unused.

BootLoader/source/read_card.c

@@ -150,10 +150,12 @@ int cardInit (tNDSHeader* ndsHeader, u32* chipID)
 		return ERR_HEAD_CRC;
 	}
 
+	/*
 	// Check logo CRC
 	if (ndsHeader->logoCRC16 != 0xCF56) {
 		return ERR_LOGO_CRC;
 	}
+	*/
 
 	// Initialise blowfish encryption for KEY1 commands and decrypting the secure area
 	init_keycode (*((u32*)&ndsHeader->gameCode), 2, 8);
@@ -257,7 +259,8 @@ int cardInit (tNDSHeader* ndsHeader, u32* chipID)
 		for (i = 0; i < 0x200; i ++) {
 			*secureArea++ = 0xe7ffdeff;
 		}
-		return normalChip ? ERR_SEC_NORM : ERR_SEC_OTHR;
+		// return normalChip ? ERR_SEC_NORM : ERR_SEC_OTHR;
+		return normalChip ? ERR_NONE : ERR_NONE;
 	}
 
 	return ERR_NONE;

Makefile

@@ -11,7 +11,7 @@ export TARGET		:=	NitroHax
 export TOPDIR		:=	$(CURDIR)
 
 export VERSION_MAJOR	:= 0
-export VERSION_MINOR	:= 97
+export VERSION_MINOR	:= 98
 export VERSTRING	:=	$(VERSION_MAJOR).$(VERSION_MINOR)
 
 #---------------------------------------------------------------------------------

arm7/source/cheat_engine_arm7.c

@@ -24,10 +24,9 @@ void runCheatEngineCheck (void)
 	{
 
 		REG_SCFG_ROM = 0x703;
-		if(fifoCheckValue32(FIFO_USER_04)) { REG_SCFG_CLK=0x0180; } else { /* Do nothing */ }
+		if(fifoCheckValue32(FIFO_USER_04)) { REG_SCFG_CLK=0x0180; }
 		REG_SCFG_EXT = 0x12A00000;
 		// REG_SCFG_EXT = 0x92A00000;
-
 
 		irqDisable (IRQ_ALL);
 		*((vu32*)0x027FFE34) = (u32)0x06000000;

arm7/source/main.c

@@ -19,32 +19,41 @@
 #include <nds.h>
 #include <nds/arm7/input.h>
 #include <nds/system.h>
-#include <nds/fifocommon.h>
 
 #include <maxmod7.h>
 
 #include "cheat_engine_arm7.h"
 
-
 void VcountHandler() {
 	inputGetAndSend();
 }
 
 void VblankHandler(void) {
 }
 
-//---------------------------------------------------------------------------------
-int main(void) {
-//---------------------------------------------------------------------------------
+void PowerOnSlot() {
 
-	REG_SCFG_CLK = 0x187;
-	// REG_SCFG_EXT |= 0x830F0100; // NAND ACCESS
-	// REG_SCFG_CLK |= 1;
+	// Power On Slot
+	while(REG_SCFG_MC&0x0C !=  0x0C); // wait until state<>3
+	if(REG_SCFG_MC&0x0C != 0x00) return; //  exit if state<>0
+
+	REG_SCFG_MC = 0x04;    // wait 1ms, then set state=1
+	while(REG_SCFG_MC&0x0C != 0x04);
+
+	REG_SCFG_MC = 0x08;    // wait 10ms, then set state=2      
+	while(REG_SCFG_MC&0x0C != 0x08);
+
+	REG_ROMCTRL = 0x20000000; // wait 27ms, then set ROMCTRL=20000000h
+
+	while(REG_ROMCTRL&0x8000000 != 0x8000000);
+
+}
 
-	// The above lines of code is not correct for arm7. That's arm9 SCFG_EXT.
-	// This is the correct setup to enable SD/NAND access on Arm7.
-	REG_SCFG_EXT = 0x93FFFB00; // NAND/SD Access
+int main(void) {
 
+	// REG_SCFG_EXT = 0x93FFFB00;
+	REG_SCFG_CLK = 0x0187;
+
 	irqInit();
 	fifoInit();
 
@@ -64,17 +73,17 @@ int main(void) {
 	irqSet(IRQ_VCOUNT, VcountHandler);
 	irqSet(IRQ_VBLANK, VblankHandler);
 
-	irqEnable( IRQ_VBLANK | IRQ_VCOUNT);   
-
+	irqEnable( IRQ_VBLANK | IRQ_VCOUNT);
+
+	// Make sure Arm9 had a chance to check slot status
 	fifoWaitValue32(FIFO_USER_01);
-	dsi_resetSlot1();
-	fifoSendValue32(FIFO_USER_02, 1);
-
-	// Keep the ARM7 mostly idle
+	// If Arm9 reported slot is powered off, have Arm7 wait for Arm9 to be ready before card reset. This makes sure arm7 doesn't try card reset too early.
+	if(fifoCheckValue32(FIFO_USER_02)) { PowerOnSlot(); }
+	fifoSendValue32(FIFO_USER_03, 1);
+
 	while (1) {
 		runCheatEngineCheck();
 		swiWaitForVBlank();
 	}
 }
 
-

arm9/source/main.cpp

@@ -52,7 +52,7 @@ int main(int argc, const char* argv[])
 {
 	dsi_forceTouchDsmode();
 
-	REG_SCFG_EXT = 0x8307F100; // NAND/SD Access
+	// REG_SCFG_EXT = 0x8307F100; // NAND/SD Access
 	REG_SCFG_CLK = 0x85;
 
 	u32 ndsHeader[0x80];
@@ -67,6 +67,10 @@ int main(int argc, const char* argv[])
 
 	ui.TWLBoostCPU=false;
 
+	// If slot is powered off, tell Arm7 slot power on is required.
+	if(REG_SCFG_MC == 0x11) { fifoSendValue32(FIFO_USER_02, 1); }
+	if(REG_SCFG_MC == 0x10) { fifoSendValue32(FIFO_USER_02, 1); }
+
 	ui.showMessage (UserInterface::TEXT_TITLE, TITLE_STRING);
 
 #ifdef DEMO
@@ -80,14 +84,10 @@ int main(int argc, const char* argv[])
 		for (int i = 0; i < 20; i++) { swiWaitForVBlank(); }
 	}
 
+	// Tell Arm7 it's ready for card reset (if card reset is nessecery)
 	fifoSendValue32(FIFO_USER_01, 1);
-
-	for (int i = 0; i < 30; i++) { swiWaitForVBlank(); }
-
-	fifoWaitValue32(FIFO_USER_02);	
-
-	for (int i = 0; i < 30; i++) { swiWaitForVBlank(); }
-
+	// Waits for Arm7 to finish card reset (if nessecery)
+	fifoWaitValue32(FIFO_USER_03);
 
 	ensure (fatInitDefault(), "SD init failed");
 

patch_ndsheader_dsiware.py

@@ -379,9 +379,8 @@ def writeBlankuntilAddress(f_out, caddr, taddr):
 			MBK_1_5_Settings= 		'\x81\x85\x89\x8d\x80\x84\x88\x8c\x90\x94\x98\x9c\x80\x84\x88\x8c\x90\x94\x98\x9c',
 			MBK_6_8_Settings_ARM7= 	'\xc07\x00\x08@7\xc0\x07\x007@\x07',
 			MBK_6_8_Settings_ARM9= 	'\x00\x00\x00\x00@7\xc0\x07\x007@\x07',
-			accessControl=			0x00000118,
-			#arm7ScfgExtMask= 		0x80000000,
-			arm7ScfgExtMask=		0x80000000,
+			accessControl=			0x00000038,
+			arm7ScfgExtMask=		0x80040000,
 			reserved_flags=			0x00000000,
 			arm7iLoadAddress= 		0x2E80000,
 			arm7iRomOffset= 		arm7iRomOffset,
@@ -391,7 +390,7 @@ def writeBlankuntilAddress(f_out, caddr, taddr):
 			arm9iSize= 				arm9isize,			
 			global_MBK_9_Setting= 	'\x0f\x00\x00\x03',	
 			iconSize=				2112,		
-			pubSaveDataSize= 		81920,
+			pubSaveDataSize= 		00000,
 			regionFlags=			'\xff\xff\xff\xff',	
 			title_id=				srlHeaderPatched.gameCode[::-1]+"\x04\x00\x03\x00",
 			twlRomSize=				srlHeaderPatched.ntrRomSize+totaldsisize,