Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

log test header for debug #16

Merged
merged 1 commit into from
Dec 20, 2024
Merged

log test header for debug #16

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
69 changes: 56 additions & 13 deletions tests/peepopt/muldiv_c.ys
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,9 @@ select -assert-any t:$div
design -reset



# Basic pattern transformed: (a * b) / c
log -pop
log -header "Basic pattern transformed: (a * b) / c"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -57,7 +58,10 @@ select -assert-count 1 t:$mul
select -assert-count 0 t:$div
design -reset

# Transformed on symmetry in multiplication

log -pop
log -header "Transformed on symmetry in multiplication"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -74,7 +78,9 @@ select -assert-count 1 t:$mul
select -assert-count 0 t:$div
design -reset

# Transformed on b == c
log -pop
log -header "Transformed on b == c"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -91,7 +97,10 @@ select -assert-count 1 t:$mul
select -assert-count 0 t:$div
design -reset

# b negative, c positive

log -pop
log -header "b negative, c positive"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -108,7 +117,10 @@ select -assert-count 1 t:$mul
select -assert-count 0 t:$div
design -reset

# b positive, c negative

log -pop
log -header "b positive, c negative"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -125,7 +137,10 @@ select -assert-count 1 t:$mul
select -assert-count 0 t:$div
design -reset

# No transform when b not divisible by c

log -pop
log -header "No transform when b not divisible by c"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -142,7 +157,10 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when product has a second fanout

log -pop
log -header "No transform when product has a second fanout"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -161,7 +179,10 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when divisor is 0

log -pop
log -header "No transform when divisor is 0"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -178,7 +199,10 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when (a*b) output can overflow (divider’s A input signed)

log -pop
log -header "No transform when (a*b) output can overflow (divider’s A input signed)"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -194,6 +218,11 @@ design -load postopt
select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset


log -pop
log -header "No transform when (a*b) output can overflow (divider’s A input signed)"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -210,7 +239,10 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when (a*b) output can overflow (divider’s A input unsigned)

log -pop
log -header "No transform when (a*b) output can overflow (divider’s A input unsigned)"
log -push
read_verilog <<EOT
module top(
input [3:0] a,
Expand All @@ -226,6 +258,10 @@ design -load postopt
select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

log -pop
log -header "No transform when (a*b) output can overflow (divider’s A input unsigned)"
log -push
read_verilog <<EOT
module top(
input [3:0] a,
Expand All @@ -242,7 +278,9 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when (a*b) and x/c fitting criteria but not connected (x != a*b)
log -pop
log -header "No transform when (a*b) and x/c fitting criteria but not connected (x != a*b)"
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -260,9 +298,11 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

# No transform when b only divisible by c if b misinterpreted as unsigned
log -pop
log -header "No transform when b only divisible by c if b misinterpreted as unsigned"
# b 1001 is -7 but 9 misinterpreted
# c 11 is 3
log -push
read_verilog <<EOT
module top(
input signed [3:0] a,
Expand All @@ -279,6 +319,9 @@ select -assert-count 1 t:$mul
select -assert-count 1 t:$div
design -reset

log -pop
log -header "Transform even if (a*b) result would overflow if divider’s A input signedness is confused & (A input is unsigned)"
log -push
# Transform even if:
# (a*b) result would overflow if divider’s A input signedness is confused
# (A input is unsigned)
Expand Down