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Convert to miter/sat #5

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Dec 18, 2024
Merged

Convert to miter/sat #5

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29 changes: 20 additions & 9 deletions tests/peepopt/multdiv_c.ys
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Original file line number Diff line number Diff line change
Expand Up @@ -2,24 +2,30 @@ log -header "Test simple positive case"
log -push
design -reset
read_verilog <<EOF
module muldiv_const_ok (
module top (
input wire [31:0] a,
output wire [63:0] y
);
assign y = (a * 5140) / (257 * 2);
endmodule
EOF
check -assert
equiv_opt -assert peepopt ;;;
design -load postopt
select -assert-any t:$mul # assert mult
copy top orig
cd top
peepopt
select -assert-none t:$div
clean -purge
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
sat -verify -prove-asserts -show-ports -enable_undef miter


log -pop
log -header "Test negative case where div is kept"
log -push
design -reset
read_verilog <<EOF
module muldiv_const_ko (
module top (
input wire signed [31:0] a,
output wire signed [63:0] y,
output wire probe
Expand All @@ -31,8 +37,13 @@ module muldiv_const_ko (
endmodule
EOF
check -assert
equiv_opt -assert peepopt ;;;
design -load postopt
select -assert-any t:$div # assert div
copy top orig
cd top
peepopt
select -assert-any t:$div
clean -purge
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
sat -verify -prove-asserts -show-ports -enable_undef miter


log -pop