FPGA-retrigger : hold for several seconds

[martino35]

Is it possible to hold a step for several seconds before receiving a retrigger signal ?

[t1mur]

Yep...it holds as long as you want. Timur

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On Thu, Feb 8, 2018 at 9:12 AM, martino35 ***@***.***> wrote: Is it possible to hold a step for several seconds before receiving a retrigger signal ? — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#26>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAwy7C5ctWR3RKrwp5qioQdPp3SJmPD3ks5tSwDQgaJpZM4R-aaN> .

[martino35]

Hello, Thank you very much for your feedback. I have a strange behaviours when the "hold-then-retrigger" option is enabled. First, in some cases, the sequence bugs after the first iteration. I did not clearly identify when it happens but it seems to depend on the following step duration and the time resolution of the step. The "event log" message is : "At least 1 daqMx task generated a different number of samples from the expected number". Secondly, in other cases the duration of the following step is affected by the "hold timeout" and sometimes it is even skipped. Finally, Cicero keeps running the sequence as usual while the "hold-then-retrigger" option is enabled. The total duration of the sequence is not modified, and it seems what is displayed on Cicero is delayed compared to what the sequence actually executes... Many thanks in advance for your assistance. Best regards Martin RABAULT PhD Student Laboratoire Photonique, Numérique & Nanosciences (LP2N) IOGS, CNRS & Université Bordeaux 1 (UMR5298) I n s titu t d'Optique d'Aquitaine Rue F rançoi s Mitterrand 33400 T alen ce (Franc e) Tel : +33 (0)6 3 8 83 37 84

----- Mail original ----- De: "t1mur" <notifications@github.com> À: "akeshet/Cicero-Word-Generator" <Cicero-Word-Generator@noreply.github.com> Cc: "martino35" <martin.rabault@institutoptique.fr>, "Author" <author@noreply.github.com> Envoyé: Vendredi 9 Février 2018 03:05:42 Objet: Re: [akeshet/Cicero-Word-Generator] FPGA-retrigger : hold for several seconds (#26) Yep...it holds as long as you want. Timur

On Thu, Feb 8, 2018 at 9:12 AM, martino35 ***@***.***> wrote: Is it possible to hold a step for several seconds before receiving a retrigger signal ? — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#26>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAwy7C5ctWR3RKrwp5qioQdPp3SJmPD3ks5tSwDQgaJpZM4R-aaN> .

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[Xiaoql]

Hi Martin, We have met the similar problem to yours. We've tried to hold a step for dozens of seconds. Above ~50s the sequence will output incorrectly. We found it's due to the limit of the Int32 during the generation of the variable timebase buffers. For a 40MHz FPGA clock, the upper bound is (2^31-1)*25ns~53.6s. One may upgrade Int32 to 64bit integers or simply copy a 50s timestep so we can hold for a longer time which is enough for most of the experiments. Besides, there is another similar limit when coping with Pulses. The Int32 will limit the total sequence length. Here we expand int to long integers. I hope this will help you. Best regards,

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-------------------------------------------------------------------------------------------------------------------- 郑永光 *（Zheng Yong-Guang） QPQI, HFNL, USTC,No.96 Jinzhai Rd. , Hefei, Anhui,230026, P. R. ChinaMobile : 0086-13063453720Email : yonggzheng@gmail.com <yonggzheng@gmail.com>* 2018-02-09 20:18 GMT+08:00 martino35 <notifications@github.com>:

Hello, Thank you very much for your feedback. I have a strange behaviours when the "hold-then-retrigger" option is enabled. First, in some cases, the sequence bugs after the first iteration. I did not clearly identify when it happens but it seems to depend on the following step duration and the time resolution of the step. The "event log" message is : "At least 1 daqMx task generated a different number of samples from the expected number". Secondly, in other cases the duration of the following step is affected by the "hold timeout" and sometimes it is even skipped. Finally, Cicero keeps running the sequence as usual while the "hold-then-retrigger" option is enabled. The total duration of the sequence is not modified, and it seems what is displayed on Cicero is delayed compared to what the sequence actually executes... Many thanks in advance for your assistance. Best regards Martin RABAULT PhD Student Laboratoire Photonique, Numérique & Nanosciences (LP2N) IOGS, CNRS & Université Bordeaux 1 (UMR5298) I n s titu t d'Optique d'Aquitaine Rue F rançoi s Mitterrand 33400 T alen ce (Franc e) Tel : +33 (0)6 3 8 83 37 84 ----- Mail original ----- De: "t1mur" ***@***.***> À: "akeshet/Cicero-Word-Generator" <Cicero-Word-Generator@ noreply.github.com> Cc: "martino35" ***@***.***>, "Author" < ***@***.***> Envoyé: Vendredi 9 Février 2018 03:05:42 Objet: Re: [akeshet/Cicero-Word-Generator] FPGA-retrigger : hold for several seconds (#26) Yep...it holds as long as you want. Timur On Thu, Feb 8, 2018 at 9:12 AM, martino35 ***@***.***> wrote: > Is it possible to hold a step for several seconds before receiving a > retrigger signal ? > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > <#26>, or mute the > thread > <https://github.com/notifications/unsubscribe-auth/ AAwy7C5ctWR3RKrwp5qioQdPp3SJmPD3ks5tSwDQgaJpZM4R-aaN> > . > — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub , or mute the thread . — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#26 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AH7v_7eFnuAuiYfcZV_5Nh8i8yMrXRcRks5tTDeYgaJpZM4R-aaN> .

[martino35]

Thank you Yong-Guang,

I don't think this is the same problem you had since even with few hundreds of ms of holding time the bug can occur... Moreover I use an external 10MHz clock for the FPGA.

The article of Aviv mentions a FPGA-polling mode in which "the FPGA-derived software clock can be broadcast over the network using a lightweight UDP stream". I think this would solve the issue but i don't see how to configure the FPGA and Atticus use this mode.