Interface binding

alainmarcel · Dec 7, 2024 · 19dbece · 19dbece
1 parent 100847c
commit 19dbece
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Showing 13 changed files with 1,982 additions and 1,535 deletions.
diff --git a/include/Surelog/Design/ModuleInstance.h b/include/Surelog/Design/ModuleInstance.h
@@ -83,6 +83,7 @@ class ModuleInstance final : public ValuedComponentI {
     }
   }
   ModuleInstance* getParent() const { return m_parent; }
+  void setParent(ModuleInstance* parent) { m_parent = parent; }
   const FileContent* getFileContent() const { return m_fileContent; }
   PathId getFileId() const;
   NodeId getNodeId() const { return m_nodeId; }

diff --git a/src/DesignCompile/CompileFileContent.cpp b/src/DesignCompile/CompileFileContent.cpp
@@ -108,8 +108,10 @@ bool CompileFileContent::collectObjects_() {
         break;
       }
       case VObjectType::paBind_directive: {
-        m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign,
-                                 nullptr);
+        if (!m_declOnly) {
+          m_helper.compileBindStmt(m_fileContent, fC, id, m_compileDesign,
+                                   nullptr);
+        }
         break;
       }
       case VObjectType::paParameter_declaration: {

diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp
@@ -660,6 +660,9 @@ ModuleInstance* DesignElaboration::createBindInstance_(
   if (instance) {
     std::vector<ModuleInstance*> parentSubInstances;
     instance->setInstanceBinding(parent);
+    if (instance->getParent() == nullptr) {
+      instance->setParent(parent);
+    }
     NodeId parameterOverloading = fC->Sibling(bindNodeId);
     if (fC->Type(parameterOverloading) ==
         VObjectType::paHierarchical_instance) {

diff --git a/tests/AssertDelayError/AssertDelayError.log b/tests/AssertDelayError/AssertDelayError.log
diff --git a/tests/AssertTempError/AssertTempError.log b/tests/AssertTempError/AssertTempError.log
diff --git a/tests/BindStmt2/BindStmt2.log b/tests/BindStmt2/BindStmt2.log
diff --git a/tests/BindingPort/BindingPort.log b/tests/BindingPort/BindingPort.log
@@ -60,28 +60,28 @@ AST_DEBUG_END
 [NTE:EL0503] ${SURELOG_DIR}/tests/BindingPort/dut.sv:4:1: Top level module "work@UART".
 [ERR:EL0550] ${SURELOG_DIR}/tests/BindingPort/dut.sv:22:38: Unknown port "state".
 [NTE:EL0508] Nb Top level modules: 1.
-[NTE:EL0509] Max instance depth: 1.
-[NTE:EL0510] Nb instances: 3.
-[NTE:EL0511] Nb leaf instances: 2.
+[NTE:EL0509] Max instance depth: 2.
+[NTE:EL0510] Nb instances: 2.
+[NTE:EL0511] Nb leaf instances: 1.
 [INF:UH0706] Creating UHDM Model...
 === UHDM Object Stats Begin (Non-Elaborated Model) ===
 design                                                 1
-logic_net                                              5
-logic_typespec                                         8
-module_inst                                            7
-port                                                   5
-ref_obj                                                7
-ref_typespec                                           8
+logic_net                                              4
+logic_typespec                                         6
+module_inst                                            5
+port                                                   4
+ref_obj                                                5
+ref_typespec                                           6
 === UHDM Object Stats End ===
 [INF:UH0707] Elaborating UHDM...
 === UHDM Object Stats Begin (Elaborated Model) ===
 design                                                 1
-logic_net                                              5
-logic_typespec                                         8
-module_inst                                            7
-port                                                   8
-ref_obj                                               12
-ref_typespec                                          11
+logic_net                                              4
+logic_typespec                                         6
+module_inst                                            5
+port                                                   6
+ref_obj                                                8
+ref_typespec                                           8
 === UHDM Object Stats End ===
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/surelog.uhdm ...
 [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BindingPort/slpp_all/checker/surelog.chk.html ...
@@ -200,17 +200,18 @@ design: (work@UART)
     |vpiInstance:
     \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
   |vpiModule:
-  \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
+  \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
     |vpiParent:
     \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
     |vpiName:uut
+    |vpiFullName:work@UART.uut
     |vpiDefName:work@UART_assertions
     |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv
     |vpiDefLineNo:13
     |vpiNet:
     \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
       |vpiParent:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
+      \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
       |vpiTypespec:
       \_ref_typespec: (work@UART.uut.clk)
         |vpiParent:
@@ -225,78 +226,24 @@ design: (work@UART)
     |vpiPort:
     \_port: (state), line:14:11, endln:14:14
       |vpiParent:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
+      \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
       |vpiName:state
       |vpiDirection:1
       |vpiHighConn:
-      \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47
+      \_ref_obj: (work@UART.clk), line:22:44, endln:22:47
         |vpiParent:
         \_port: (state), line:14:11, endln:14:14
         |vpiName:clk
-        |vpiFullName:work@UART.uut.state.clk
+        |vpiFullName:work@UART.clk
         |vpiActual:
         \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
       |vpiLowConn:
-      \_ref_obj: (uut.clk), line:22:38, endln:22:43
+      \_ref_obj: (work@UART.uut.clk), line:22:38, endln:22:43
         |vpiParent:
         \_port: (state), line:14:11, endln:14:14
         |vpiName:clk
-        |vpiFullName:uut.clk
-        |vpiActual:
-        \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
-      |vpiTypedef:
-      \_ref_typespec: (work@UART.uut.state)
-        |vpiParent:
-        \_port: (state), line:14:11, endln:14:14
-        |vpiFullName:work@UART.uut.state
-        |vpiActual:
-        \_logic_typespec: , line:14:11, endln:14:11
-      |vpiInstance:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
-  |vpiModule:
-  \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
-    |vpiParent:
-    \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
-    |vpiName:uut
-    |vpiDefName:work@UART_assertions
-    |vpiDefFile:${SURELOG_DIR}/tests/BindingPort/dut.sv
-    |vpiDefLineNo:13
-    |vpiNet:
-    \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
-      |vpiParent:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
-      |vpiTypespec:
-      \_ref_typespec: (work@UART.uut.clk)
-        |vpiParent:
-        \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
         |vpiFullName:work@UART.uut.clk
         |vpiActual:
-        \_logic_typespec: , line:14:11, endln:14:11
-      |vpiName:clk
-      |vpiFullName:work@UART.uut.clk
-    |vpiInstance:
-    \_module_inst: work@UART (work@UART), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:4:1, endln:10:10
-    |vpiPort:
-    \_port: (state), line:14:11, endln:14:14
-      |vpiParent:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
-      |vpiName:state
-      |vpiDirection:1
-      |vpiHighConn:
-      \_ref_obj: (work@UART.uut.state.clk), line:22:44, endln:22:47
-        |vpiParent:
-        \_port: (state), line:14:11, endln:14:14
-        |vpiName:clk
-        |vpiFullName:work@UART.uut.state.clk
-        |vpiActual:
-        \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
-      |vpiLowConn:
-      \_ref_obj: (uut.clk), line:22:38, endln:22:43
-        |vpiParent:
-        \_port: (state), line:14:11, endln:14:14
-        |vpiName:clk
-        |vpiFullName:uut.clk
-        |vpiActual:
         \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
       |vpiTypedef:
       \_ref_typespec: (work@UART.uut.state)
@@ -306,17 +253,13 @@ design: (work@UART)
         |vpiActual:
         \_logic_typespec: , line:14:11, endln:14:11
       |vpiInstance:
-      \_module_inst: work@UART_assertions (uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
+      \_module_inst: work@UART_assertions (work@UART.uut), file:${SURELOG_DIR}/tests/BindingPort/dut.sv, line:22:17, endln:22:50
 \_weaklyReferenced:
 \_logic_typespec: , line:5:11, endln:5:11
 \_logic_typespec: , line:5:11, endln:5:11
   |vpiParent:
   \_logic_net: (work@UART.clk), line:5:11, endln:5:14
 \_logic_typespec: , line:14:11, endln:14:11
-\_logic_typespec: , line:14:11, endln:14:11
-  |vpiParent:
-  \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
-\_logic_typespec: , line:14:11, endln:14:11
 \_logic_typespec: , line:14:11, endln:14:11
   |vpiParent:
   \_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14